Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-05-27
1999-12-21
Fourson, George
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438585, 438592, 438952, H01L 21336
Patent
active
060048530
ABSTRACT:
A process for fabricating a straight walled, silicon nitride capped, gate structure, for a MOSFET device, has been developed. The process features the creation of a straight walled, photoresist shape, to be used as an etch mask, during the patterning of the straight walled, silicon nitride capped, gate structure. A silicon oxynitride layer, with a specific thickness range between about 820 to 920 Angstroms, is used as a bottom anti-reflective coating, (BARC), layer, located between an overlying straight walled, photoresist shape, and an underlying silicon nitride capping layer. The BARC layer retards the reflection emitted from a silicon nitride capping layer, during the photolithographic exposure procedure, used for definition of the straight walled, photoresist shape, allowing the desired straight walled, photoresist shape, to be obtained, independent of the thickness of the silicon nitride capping layer. The ability to fabricate straight walled, silicon nitride capped, gate structures, allows control, and uniformity, of channel regions, located underlying the straight walled, silicon nitride capped, gate structure, and between source/drain regions, self-aligned to the straight walled, silicon nitride capped, gate structures, to be realized.
REFERENCES:
patent: 5600165 (1997-02-01), Tsukamoto et al.
patent: 5907781 (1999-05-01), Chen et al.
patent: 5937319 (1999-08-01), Xiang et al.
Lin Yeh-Sen
Yang Hsiao-Ying
Ackerman Stephen B.
Fourson George
Saile George O.
Vanguard International Semiconductor Corporation
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