Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-13
2003-04-08
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S652000, C438S688000, C438S783000, C438S952000
Reexamination Certificate
active
06544882
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to semiconductor integrated circuits and more specifically to a method of fabrication used for semiconductor integrated circuit devices, whereby the reliability and interlevel adhesion of multilayer structures of FSG (F-doped SiO
2
) dielectric layers and aluminum-copper-TiN conducting layers are improved.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits multilayer structures of dielectric layers and patterned conducting layers are used to form the interconnections between discrete devices formed in/on a semiconductor substrate. Depending upon the levels of integration required, one or more conducting layers with the appropriate interconnection patterns are formed alternately with interlevel dielectric layers and connections between the metal layers are provided through “via plugs” or “via studs”. Typically in highly dense, sub micron-size integrated circuit devices, where small features are desired, three, four or more levels of interconnection metallization may be required.
Therefore, it is imperative that the multiple layers of dielectric materials and conducting materials be compatible in terms of mutual adhesion and chemical stability. Also, manufacturing processes for the individual layers, such as deposition and pattern formation processes, must be compatible with both previously deposited layers and with subsequently deposited layers and the steps of forming thereof.
One problem encountered when using FSG (F-doped SiO
2
) dielectric layers in multilevel integrated circuit structures is that F atoms incorporated in the FSG layers have high mobility and affinity to moisture. During integrated circuit processing the mobility of the F atoms and the affinity of F atoms to moisture cause the formation of HF at interfaces between FSG and deposited conducting layers such as aluminum-copper or aluminum and aluminum-copper or aluminum having a surface layer of TiN, used as an ARC (Anti Reflection Coating) layer. The formation of HF at the interfaces allows reaction of the HF with the metal layers. The reaction of HF with the metal layers causes corrosion of the aluminum-copper or aluminum conducting layers and attack of unreacted Ti within the TiN ARC layer. Both the corrosion of the aluminum-copper or aluminum conducting layers and the attack of unreacted Ti within the TiN ARC layer cause reduced adhesion of FSG to the metal layer and delamination of the FSG layer from the metal layer. This delamination usually appears during subsequent thermal cycling processing steps and manifests itself in the form of bubbles or micro areas of delamination between the FSG layer and metal layer. Such loss of adhesion and delamination are unacceptable and result in low manufacturing process yield. Furthermore, interfaces which are susceptible to reaction between HF and metal layers are sources of reliability degradation and can thus cause premature failure of the integrated circuit devices.
It is, therefore, desirable to have a manufacturing process for formation of a FSG (F-doped SiO
2
) dielectric layer over a patterned aluminum-copper-TiN interconnection layer that produces good adhesion between the FSG layer and aluminum-copper and/or TiN layers and is free of delamination between the FSG layer and the aluminum-copper-TiN layer. The integrity of the interfaces between the FSG layers and aluminum-copper-TiN layers must be maintained throughout the manufacturing processes for multilevel integrated circuits, such manufacturing processes requiring multiple thermal cycles for the formation of multilevel patterns of aluminum-copper-TiN embedded in FSG dielectric layers.
Numerous patents teach methods of treating TiN layers to result in improved TiN properties, as recited in the following referenced patents. U.S. Pat. No. 5,874,355 entitled “Method To Prevent Volcano Effect In Tungsten Plug Deposition” granted Feb. 23, 1999 to Ji-Chung Huang et al. teaches a N
2
plasma treatment of a TiN/Ti bilayer to stuff the grain boundaries of the TiN layer with N
2
.
U.S. Pat. No. 5,759,916 entitled “Method For Forming A Void-Free Titanium Nitride Anti-Reflective Coating (ARC) Layer Upon An Aluminum Containing Conductor Layer” granted Jun. 2, 1998 to Te-Ming Hsu et al. describes a method of forming a void-free titanium nitride layer upon an aluminum conductor layer. The titanium nitride layer comprises a first layer of titanium rich titanium nitride and a second layer of stoichiometric titanium nitride. Together, the titanium rich titanium nitride layer and the stoichiometric titanium nitride layer form the void-free titanium nitride.
U.S. Pat. No. 5,688,717 entitled “Construction That Prevents The Undercut Of Interconnect Lines In Plasma Metal Etch Systems” granted Nov. 18, 1997 to Lewis Shen et al. shows a Ti
x
N
y
layer, not necessarily stoichiometric, in combination with a TiN layer interposed between oxide and aluminum layers to improve the adhesion of the aluminum layer to the oxide layer.
U.S. Pat. No. 5,652,464 entitled “Integrated Circuit With A Titanium Nitride Contact Barrier Having Oxygen Stuffed Grain Boundaries” granted Jul. 29, 1997 to De-Dui Liao et al. shows a barrier layer overlying a silicide film, where the barrier layer includes titanium oxynitride and titanium nitride.
U.S. Pat. No. 5,895,266 entitled “Titanium Nitride Barrier Layers” granted Apr. 20, 1999 to Jianming Fu et al. describes a composite barrier layer formed by sequentially sputter depositing a first titanium layer, oxidizing this titanium layer, sputter depositing a titanium nitride layer, oxidizing the titanium nitride layer, and optionally depositing an overlying titanium wetting layer.
U.S. Pat. No. 5,700,737 entitled “PECVD Silicon Nitride For Etch Stop Mask And Ozone TEOS Pattern Sensitivity Elimination” granted Dec. 23, 1997 to Chen-Hun Yu et al. shows a TiN ARC (Anti Reflection Coating) layer over aluminum.
The present invention is directed to a novel method of forming a FSG (F-doped SiO
2
) dielectric layer over a patterned aluminum-copper-TiN interconnection layer that produces good adhesion between the FSG layer and aluminum-copper and/or TiN layers and is free of delamination between the FSG layer and the aluminum-copper-TiN layer.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of forming an integrated circuit having FSG (F-doped SiO
2
) as the dielectric layer in multilevel interconnection structures in combination with patterned aluminum-copper-TiN conductors, in which the adhesion between the FSG (F-doped SiO
2
) dielectric layer and the aluminum-copper-TiN pattern is improved.
A more specific object of the present invention is to provide an improved method of forming an integrated circuit having FSG (F-doped SiO
2
) as the dielectric layer in multilevel interconnection structures in combination with patterned aluminum-copper-TiN conductors, in which F atoms residing in the FSG dielectric layer are prevented from reacting with the patterned aluminum-copper-TiN conductor and causing delamination between the FSG layer and the patterned aluminun-copper-TiN layer.
Another object of the present invention is to provide an improved method of forming an integrated circuit having FSG (F-doped SiO
2
) as the dielectric layer in multilevel interconnection structures in combination with patterned aluminum-copper-TiN conductors, whereby the TiN overlying the aluminum-copper is rendered impervious to F atoms residing in the FSG layer.
In accordance with the present invention, the above and other objectives are realized by using a method of fabricating a void-free titanium nitride protective layer on the surface of an aluminum-copper layer, comprising the steps of: providing a semiconductor substrate having a layer of aluminum-copper deposited thereon and having a TiN ARC (Anti-Reflection Coating) layer deposited onto the layer of aluminum-copper; and exposing the TiN ARC (Anti-Reflection Coating) layer to a plasma containing N
2
and H
2
or N
2
and N
Liu Chung-Shi
Shue Shau-Lin
Yu Chen-Hua
Ackerman Stephen B.
Goudreau George
Saile George O.
Taiwan Semiconductor Manufacturing Company
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