Method to improve performance of SRAM cells, SRAM cell, SRAM...

Details Method to improve performance of SRAM cells, SRAM cell, SRAM... Method to improve performance of SRAM cells, SRAM cell, SRAM...

2007-06-29

2009-12-01

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189090, C365S203000, C365S189140, C365S189150

Reexamination Certificate

active

07626851

ABSTRACT:
A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.

REFERENCES:
patent: 5646885 (1997-07-01), Matsuo et al.
patent: 5757696 (1998-05-01), Matsuo et al.
patent: 7190609 (2007-03-01), Yamaoka et al.
patent: 2002/0186581 (2002-12-01), Yamaoka et al.
patent: 2003/0063494 (2003-04-01), Kurosaki
patent: 2005/0024917 (2005-02-01), Yamaoka et al.

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