Method to improve nitride floating gate charge trapping for...

Details Method to improve nitride floating gate charge trapping for... Method to improve nitride floating gate charge trapping for...

2000-11-09

2002-09-03

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S263000, C438S264000

Reexamination Certificate

active

06444521

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a nitride floating gate for NROM flash memory device, and more particularly to the method for the NROM flash memory device having the SiON as the floating gate.
BACKGROUND OF THE INVENTION
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEROM.
The Semiconductor ROM device, however, suffers from the disadvantage of not being a electrically programmable memory device. The programming of a ROM occurs during one of the manufacturing steps using special masks containing the data to be stored. Thus, the entire contents of a ROM must be determined before manufacture. Furthermore, the penalty is the inability to change the data once the masks are committed. If mistakes in the data programming are found they are typically very costly to correct. Any inventory that exists having incorrect data programming is instantly obsolete and probably cannot be used.
The EPROM semiconductor devices eliminate the necessity of mask programming the data. An advantage of EPROMs is that they are electrically programmed, but for erasing. The EPROMs require exposure to ultraviolet (UV) light. These devices are constructed with windows transparent to UV light to allow the die to be exposed for erasing, which must be performed before the devices can be programmed. A major drawback to these devices is that they lack the ability to be electrically erased. In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming.
The EEPROM semiconductor devices eliminate the disadvantages described above, and they can be erased and reprogrammed in-circuit. Thus, the widespread use of EEPROM semiconductor memory has prompted much research focusing on improving current technology. Active areas of research have focused on developing an EEPROM memory cell that has improved performance characteristics such as shorter programming times, utilizing lower voltages for programming and reading, longer data retention times and smaller physical dimensions.
Referring to
FIG. 1
, a profile shows an EEPROM cell of the prior art. The cell
30
comprises a P-type substrate
26
, two N
+
junctions
22
,
24
, a floating gate
14
sandwiched between two oxide layers
12
,
16
, and a control gate
18
on the top of the cell
30
. The floating gate and the control gate of EEPROM cell in the prior art are polysilicon of conductible.
When the different voltages are applied to the control gate
18
, and two N
+
junctions
22
,
24
, the hot electrons are injected to the floating gate
14
, and remain stored there. According to this method, one cell is programmed.
The floating gate
14
of the EEPROM in the prior art is polysilicon, so that the charges that get injected into the floating gate
14
are distributed equally across the entire floating gate. The threshold of the entire floating gate
14
starts to increase as more and more charges are injected into the floating gate
14
. The threshold voltage increases because the electrons that become stored in the gate screen the gate voltage from the channel. Thus, an increase in the gate threshold voltage causes the current flowing through the channel to decrease. This reduces programming efficiency by lengthening the programming time.
U.S. Pat. No. 5,768,192, issued to Boaz Eitan, teaches a non-volatile semiconductor memory cell utilizing asymmetrical charge trapping. The structure of the memory cell is similar to the EEPROM in the prior art, but the floating gate is replaced by SiN (silicon nitride). An ONO (oxide-nitride oxide) is formed above the channel area, that as NROM (nitride ROM). The nonconducting SiN layer can trap the hot electrons, and the trapped electrons cannot spread through the SiN layer because of the low conductivity of the SiN layer. Because of the asymmetrical distribution, the NROM is programmed and read asymmetrically. This means that programming and reading occur in opposite directions of the two N
+
junctions. But, the charge trapping of SiN film floating gate is not so efficiency for hot electrons and the charge distribution is wider. The disadvantages above will affect the characters of the NROM and cause the problems in programming and erasing.
Also, the conventional batch progresses are more complex. For example, the first oxide layer (tunnel oxide) is produced by heating in a furnace with high thermal temperatures of 900~1050° C., then LPCVD SiN is deposited in the furance at 800° C., is cleaned, then a high thermal budget is used to grow oxide layer top of the SiN layer by 950° C. wet thermal oxidation, then is RCA cleaned before LPCVD doped polysilicon.
Due to the complex batch process, some defects like wafer damage by misprocesses occur and, more particles are generated during the clean-up step. Furthermore, longer process queue time and more process bottlenecks cause more process cycle time and less product output.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a method to improve nitride floating gate charge trapping for NROM flash memory device. The present invention uses the SiON to replace the SiN of the NROM floating gate in the prior art. So that, the endurance and the reliability of the device are improved, and the data retention times are also extended.
It is another objective of this invention to provide an integrated process to fabricate the NROM flash memory device. Using the process, the steps of fabricating the NROM are reduced efficiently, and the defects caused by the clean steps are eliminated.
In accordance with the foregoing and other objects of this invention, a NROM flash memory is provided. A P type semiconductor substrate comprises a first N
+
doped region and a second N
+
doped region, a channel being formed in the space between the first N
+
doped region and the second N
+
doped region within the P type semiconductor substrate. A first oxide layer is overlaid and covers the channel portion of the P type semiconductor substrate. A SiON layer is formed on and overlays the first oxide layer. A second oxide layer is formed on and overlaid the SiON layer. A polysilicon layer is formed on and overlays the second oxide layer.
In accordance with the foregoing and other objects of this invention, this invention provides a SiON layer as a floating gate of the NROM flash memory.
In accordance with the foregoing and other objects of this invention, this invention provides a method using an integrated process to fabricate the NROM flash memory, comprising the following steps: providing a single wafer thermal consecutive process system to a semiconductor substrate; using a APCVD to form a first oxide layer on and overlaying said semiconductor substrate; using a PECVD to form a SiON layer on and overlaying said first oxide layer; using a LPCVD to form a second oxide layer on and overlying said SiON layer; and using a LPCVD to form a polysilicon layer on and overlying said second oxide layer.


REFERENCES:
patent: 5768192 (1998-06-01), Eitan
patent: 5801076 (1998-09-01), Ghneim et al.
patent: 5805013 (1998-09-01), Ghneim et al.
patent: 5808353 (1998-09-01), Fuller et al.
patent: 5811865 (1998-09-01), Hodges et al.
patent: 6037639 (2000-03-01), Ahmad
patent: 6249460 (2001-06-01), Forbes et al.

Affiliated with

Also associated with

Rating

Method to improve nitride floating gate charge trapping for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to improve nitride floating gate charge trapping for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to improve nitride floating gate charge trapping for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2817187