Method to improve integrated circuit defect limited yield

Details Method to improve integrated circuit defect limited yield Method to improve integrated circuit defect limited yield

1999-07-12

2001-10-09

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06301690

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to integrated circuit (IC) manufacturing yield, and more particularly to methods to improve IC defect-limited yield (DLY) by reducing particle-induced defects while accounting for IC physical design and IC manufacturing processes.
BACKGROUND OF THE INVENTION
The yield of a manufacturing process is the ratio of the product that meets or exceeds its functional and performance specifications to the total product made. Regarding integrated circuit (IC) yield, two types are defined: defect-limited yield (DLY) and circuit-limited yield (CLY). DLY is the ratio of the product that meets functional performance specification to the total product made. CLY is the ratio of the product that meets or exceeds functional performance specification to the total product made.
Particle defects reduce DLY and CLY. If a particle defect prevents the IC from functioning, DLY is reduced. If a particle defect only retards performance, then CLY is reduced.
An example of a particle defect is when a conductive particle falls between two adjacent wires on an IC, and the particle is of sufficient size to contact both wires. Such an occurrence can cause a short circuit in the IC, preventing the IC from functioning and reducing DLY.
The probability of a short circuit caused by a particle defect is proportional to the ratio of the area occupied by the circuit wiring to the total area of the IC. Thus, reducing wiring area reduces the probability of a short circuit caused by a particle defect improving DLY.
Reducing the width of individual conductors within an IC is one way of reducing overall wiring area. However, reducing the width of a conductor increases its resistance, with undesirable effects on associated voltages and IC electrical performance. Further, in a multilayer integrated circuit, reliably interconnecting the wiring layers through vias requires that the conductor have a width the size of the via opening, thereby limiting the reduction in size.
Nothing in the prior art appears to include a method of reducing wiring area without reducing IC electrical performance, and more specifically to address the problem of reduction in DLY due to short circuits caused by particle defects.
SUMMARY OF THE INVENTION
A method is provided for improving the defect-limited yield for integrated circuits. The method includes selectively reducing the wiring area of a set of conductors on an integrated circuit, to lower the probability of a short circuit occurring due to particle defects. The method reduces the wiring area by reducing the individual conductor widths on the integrated circuit while maintaining a larger width at the ends of each individual conductor so that they may be connected to off-chip connections, or to interlayer vias.
In accordance with the invention, a method is provided to determine the size of conductors which will improve the defect-limited yield, while maintaining signal voltages and currents to be carried by the conductors within an allowed variation. Each conductor may be represented as an electrical element of a network, the end points of the conductor representing nodes within the network. The voltages at each end of a conductor, and current through the conductor, is compared with a reference voltage and current, representing the minimum value which produces acceptable circuit responses. The reference voltages and currents are selected to provide an acceptable noise margin for the circuit to function. The width of each conductor is varied over a portion thereof, and a final width is selected which produces voltages and currents equal to the reference voltages and current.
The method according to the invention may be implemented as a series of computer executable instructions which determines from the various conductor lengths and widths various nodal voltages. The computer executable instructions compare the computed nodal voltages at each end of a conductor with a critical value of voltage. The value of the conductance of each conductor is iteratively decreased until the resultant conductance values produce the critical value of voltages. The effective width of each conductor may then be calculated by additional executable instructions for the determined conductances.
The invention also provides a conductor grid for an integrated circuit having individual circuit conductors having at least along a portion thereof a minimum width which improves defect yield due to particle contamination. The reduced cross section for each conductor element is established by determining a minimum voltage across the circuit conductor necessary for adequate noise immunity for any signal carried by the conductor.


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