Method to improve cell performance in split gate flash EEPROM

Details Method to improve cell performance in split gate flash EEPROM Method to improve cell performance in split gate flash EEPROM

1998-03-06

2001-02-27

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C438S291000

Reexamination Certificate

active

06194269

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a read only memory (“ROM”) cell, and more particularly to the manufacture of a flash electrically-erasable programmable read only memory (“Flash EEPROM”) cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as random access memory (RAM), mask ROMs, microcontrollers, microprocessors, application specific integrated circuits, among others.
Read only memories (ROMs) and various methods of their manufacture are known in the art. In the fabrication of a ROM, particularly an EEPROM, it is necessary to fabricate a storage cell that maintains data after the applied power is turned off, that is, a storage cell having almost permanent data characteristics. The storage cells are generally mass data storage files where each cell corresponds to the presence or absence of a stored charge on a “floating” gate of a storage cell transistor. Specifically, the storage cell includes at least two conducting layers—one conducting layer is the floating gate of the storage cell transistor, and another conducting layer is the control gate (or erase gate) for control of the cell operation—which may be, for example, polysilicon. In an exemplary typical split gate flash EEPROM device, the first gate is formed on a thin gate oxide on the substrate, and part of the split gate is formed on the thin gate oxide and the other part of the split gate is formed over the first gate. In such a device, these gates are isolated from each other by a thin dielectric layer known as an “interpoly oxide”, which may be composed of oxide or oxide
itride/oxide (“ONO”). In some typical EEPROMs, data is programmed into the cells by applying a high voltage to the control gate to inject hot electrons (or tunnel electrons in some devices) into the floating gate, and data is erased by electrons being drawn from the floating gate through a portion (often referred to as “tunnel oxide”) of the gate oxide by the Fowler-Nordheim tunneling mechanism. The process of programming data is often called coding.
In some of these particular types of split gate flash EEPROMs, a thin gate oxide is formed on the substrate. Then, a first conducting layer is formed on the thin gate oxide, patterned to form first gate electrodes. An interpoly oxide is grown over the first gate electrodes. Then, a second conducting layer is formed over the interpoly oxide and patterned to form split gate electrodes, which partially overly the first gate electrodes.
Often, in such a device, a threshold voltage (“V
t
”) adjust ion implant is performed prior to forming the gate electrodes in order to set the threshold voltage for the transistor (e.g., NMOS) channel region under the gate electrodes used as the select/control gate and the floating gate. Because the select/control gate is used for operation of the NMOS transistor which requires a predetermined threshold voltage, the threshold voltage adjust ion implant step is performed simultaneously to adjust the threshold voltage under both the floating gate and the select/control gate. Typically in the split gate cell, this threshold voltage adjust ion implant is predetermined by the requirements for the transistor with the select/control gate, thereby leaving little room for adjustment of the threshold voltage under the floating gate. That is, the threshold voltage under the select gate cannot be too low; otherwise, there will be leakage problems. However, the threshold voltage under the floating gate does not have such a limitation. In fact, the lower the threshold voltage under the floating gate is, the higher the cell current that can be obtained. The cell current is desired to be as high as possible, as long as the cell can still be programmed. Although it is desirable that the cell current be as high as possible in order to improve cell erase performance, the threshold voltage under the select gate often limits the ability to adjust the threshold voltage under the floating gate. Conventional approaches to improving cell erase performance have been to improve the electron tunneling efficiency by decreasing the tunnel oxide thickness or by increasing the gate coupling ratio (“GCR”). However, these conventional approaches undesirably result in cell reliability problems or larger cell size. In particular, decreased tunnel oxide thickness results in cell reliability problems, especially over time with multiple erase cycles, and an increased GCR of the storage cell results in an increased size of the gates and overall increase in the cell size (and therefore die size, resulting in lower device yield per wafer). Techniques for improving cell performance are important, especially since design rules for devices are becoming increasingly smaller and the requirements for device speed and performance are increasing.
From the above it is seen that an improved method of fabricating semiconductor ROM devices with reliable and improved cell performance is desired.
SUMMARY OF THE INVENTION
The present invention provides a method and resulting structure for an integrated circuit device having improved cell performance. In particular, the present invention provides an improved ROM integrated circuit and method of manufacture therefor.
According to an embodiment, the present invention provides a method of forming a semiconductor device. The method includes the steps of providing a semiconductor substrate, forming a thin oxide layer on said semiconductor substrate, and introducing first impurities into a first region of said semiconductor substrate where a first gate electrode is to be formed and into a second region of the semiconductor substrate where a split gate electrode is to be formed. The first introducing step adjusts a first threshold voltage in the first region. The method also includes the steps of forming a first gate electrode on the thin oxide layer, and introducing second impurities into the second region of the semiconductor substrate where the split gate electrode is to be formed and not into the first region. The first gate electrode has a top surface and a side surface, and the second introducing step adjusts a second threshold voltage in the second region. The method further includes steps of forming a dielectric layer over the top surface and the side surface of the first gate electrode, and forming the split gate electrode on at least a portion of the dielectric layer formed over the first gate electrode and over the second region.
Benefits of the various embodiments include the ability to provide ROM semiconductor devices which achieve better cell performance without the need to decrease the tunnel oxide thickness or increase cell size for comparable performance. The present invention is especially useful for split gate cell flash EEPROM devices with increasingly small geometries.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.


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