Method to implement stress free polishing

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S633000, C438S687000, C438S691000, C438S692000, C257SE21495

Reexamination Certificate

active

07544606

ABSTRACT:
A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar surface over the low-k dielectric layer using spin-on method, and stress free polishing the metal layer. Preferably, the metal layer comprises copper or copper alloys. The metal layer preferably includes a first sub layer having a substantially non-planar surface and a second sub layer having a substantially planar surface on the first sub layer.

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Murakami, H., et al., “Spin-on Cu Films for Ultralarge Scale Integrated Metallization,” J. Vac. Sci. Technol. B 17(5), Sep./Oct. 1999, pp. 2321-2324.
Pallinti, J., et al., “An Overview of Stress Free Polishing of Cu with Ultra Low-k (k<2.0) Films,” Interconnect Technology Conference, 2003 International Proceedings of the IEEE, 3 pages.

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