Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-03-26
1999-12-07
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438303, 438299, 438592, 438630, 438649, 438647, 438651, 438655, 438657, 438664, 438682, 438684, H01L 21283
Patent
active
059982861
ABSTRACT:
The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.
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Chen Shu-Jen
Hsu Chih-Ching
Kuo Jacky
Lin Jiunn-Hsien
Bowers Charles
Nguyen Thanh
United Semiconductor Circuit Corp.
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