Method to form transistors and local interconnects using a...

Details Method to form transistors and local interconnects using a... Method to form transistors and local interconnects using a...

2000-04-24

2001-03-20

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S655000

Reexamination Certificate

active

06204137

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming MOS transistors and local interconnects in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
In the prior art, the method used to form MOS transistors is sequentially separate from that used to form the isolation structures that surround the transistors. The shallow trench isolation (STI) method is independent and preceeds the transistor method.
Referring now to
FIG. 1
, a cross section of prior art integrated circuit device is shown. This cross section illustrates the typical sequence in the prior art. A semiconductor substrate
10
is provided. A pad oxide layer
14
is formed overlying the semiconductor substrate
10
. A silicon nitride layer
18
is deposited overlying the pad oxide layer
14
. A masking operation is used to define a pattern of active areas. Trenches
22
are etched through the silicon nitride layer
18
, and the pad oxide layer
14
, and into the semiconductor substrate
10
where shallow trench isolations (STI) are planned. The STI will serve as boundaries for the active device areas. A trench filling oxide (not shown) is deposited to fill the trenches. The silicon nitride layer
18
and pad oxide layer
14
are etched away and the trench filling oxide is planarized to complete the STI regions.
Referring now to
FIG. 2
, the next step in the prior art processing sequence is illustrated. Note first the completed STI structures
26
. A gate oxide layer
30
is formed overlying the semiconductor substrate
10
. A polysilicon layer
34
is deposited overlying the gate oxide layer
30
. The polysilicon layer
34
and the gate oxide layer
30
are then patterned using a masking process to form the gate electrode of the planned MOS transistor.
Referring now to
FIG. 3
, the device is shown after further processing. Lightly doped drain (LDD) regions
42
and heavily doped drains and sources
38
are implanted into the semiconductor substrate
10
. Sidewall spacers
46
are formed adjacent to the gate electrode
34
. Two observations may be made concerning the typical device shown in FIG.
3
. First, the STI regions
26
often exhibit junction leakage problems near the edge
50
of the STI for a variety of well-known reasons including problems with etching defects and substrate stress as well as problems with the planarization process (polishing). Second, the fact that the polysilicon layer
34
is deposited overlying only the very thin gate oxide layer
30
means that all of the polysilicon layer
34
overlying the active area of the substrate (between the STI structures
26
) is effectively a gate electrode. This means that any use of the polysilicon layer
34
as a local interconnect must be done outside of the active area.
Referring now to
FIG. 4
, the impact of the second observation is made clearer. A top view of the prior art device is shown. The polysilicon layer
34
is shown intersecting a rectangle
54
which represents the active area inside of the STI regions. The intersection between the polysilicon layer
34
and the active area
54
is the gate electrode of the transistor. A metal interconnecting layer
58
is shown connecting to the polysilicon layer
34
through a contact opening
62
. Note that the processing sequence and approach of the prior art requires that the contact
62
between the polysilicon layer
34
and the metal interconnect layer
58
be made outside of the active area
54
. This layout rule uses precious space in the integrated circuit.
Several prior art approaches disclose methods to form transistors and shallow trench isolations in the manufacture of an integrated circuit device. U.S. Pat. No. 5,856,225 to Lee et al discloses a method to form a MOSFET with a self-aligning channel. A temporary or dummy gate is formed from a stack of pad oxide, polysilicon, and a capping insulator. After formation of source and drain junctions, the dummy gate is removed. The threshold voltage and the anti-punchthrough implants are then performed. After gate oxide formation, a new polysilicon layer is deposited and polished down to form the permanent gate. Notably, since the polysilicon gate is here defined by polishing down, connections to the metal layer must be made outside the active area. Connectivity between metal and polysilicon over the gate region must be avoided due to metal migration, spiking, and reliability concerns. U.S. Pat. No. 5,786,255 to Yeh et al teaches a method to form a MOSFET with STI structures. A thick silicon nitride layer is deposited overlying the semiconductor substrate. Openings are etched through the silicon nitride layer where transistors are planned. After formation of gate oxide and silicide, the nitride is removed. Drains and sources are then implanted. U.S. Pat. No. 5,915,183 to Gambino et al discloses a method to form silicided drains and sources. A thick silicon nitride layer is deposited over the semiconductor substrate. Openings are etched through the silicon nitride layer for planned transistor gates. Polysilicon is deposited and planarized. The silicon nitride layer is etched to form sidewall spacers on the polysilicon gate and the STI. Raised polysilicon source and drain regions are formed. The drain and source junctions are then formed in the second polysilicon layer. U.S. Pat. No. 5,915,181 to Tseng discloses a process to form deep sub-micron MOSFETS. An opening is etched into an insulator layer for planned transistor gates. The gate electrode is formed in the opening. The insulator layer is then removed to thereby complete the gate electrode of the MOSFET device. U.S. Pat. No. 5,686,321 to Ko et al teaches a process to form a transistor where an opening is formed in the silicon nitride where the gate electrode is planned. After threshold implant, the opening is filled with polysilicon. The silicon nitride layer is then removed, and the polysilicon gate remains.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming MOS transistors in the manufacture of integrated circuits.
Another further object of the present invention is to provide a method to form both the MOSFET transistor electrodes and local interconnects from the same layer.
A yet further object of the present invention is to allow the local interconnect layer to be contacted within the active device area.
Another object of the present invention is to use a single silicon nitride layer for defining the shallow trench isolation trenches and for defining the gate electrode dimensions.
Another object of the present invention is to improve the characteristics of the shallow trench isolations.
In accordance with the objects of this invention, a new method of forming MOS transistors in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. The silicon nitride layer, pad oxide layer, and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations. A trench liner oxide layer is grown on the exposed semiconductor substrate inside of the trenches. A trench oxide layer is deposited overlying the silicon nitride layer and filling the trenches. The trench oxide layer is polished down to the silicon nitride layer to complete the shallow trench isolations. The silicon nitride layer is patterned to form dummy gates where the transistor gates are planned. An oxide liner layer is deposited overlying the dummy gates, the shallow trench isolations, and the semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted into the semiconductor substrate to form the drain and source junctions.

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