Method to form polycide local interconnects between narrowly-spa

Details Method to form polycide local interconnects between narrowly-spa Method to form polycide local interconnects between narrowly-spa

1999-07-16

2000-07-25

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438592, 438597, H01L 218242

Patent

active

060936029

ABSTRACT:
A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.

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patent: 5945738 (1999-08-01), Nguyen et al.
patent: 5989987 (1999-11-01), Kuo

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