Method to form non-volatile memory cells

Details Method to form non-volatile memory cells Method to form non-volatile memory cells

2000-05-09

2002-03-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S262000, C438S264000

Reexamination Certificate

active

06362045

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming non-volatile memory cells in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Non-volatile memory cells are an important device type in the art of integrated circuit manufacturing. Non-volatile memory cells, such as flash EEPROMs, are used to hold vital data and programming information in computer systems for a variety of applications. Manufacture of non-volatile memory devices presents unique challenges.
Referring now to
FIG. 1
, a non-volatile memory cell is illustrated. Many such cells would be formed in a typical non-volatile memory integrated circuit device. A semiconductor substrate
10
is shown with shallow trench isolations (STI)
12
defining the device active area. The defining element of the non-volatile memory cell is the presence of a floating gate
18
. A very thin tunneling oxide layer
14
overlies the semiconductor substrate
10
. The floating gate
18
is formed overlying the tunneling dielectric
14
. The floating gate
22
is comprised of a conductive material, such as doped polysilicon, that is not connected to any other circuit element. A stack of dielectric material, called the interpoly dielectric
22
,
26
, and
30
, overlies the floating gate
18
. The interpoly dielectric is typically composed of an oxide-nitride-oxide stack (O—N—O) comprising a bottom silicon dioxide layer
22
, a silicon nitride layer
26
, and a top silicon dioxide layer
30
. Finally, a control gate
34
, of conducting material such as polysilicon, overlies the second silicon dioxide layer
30
. The topology of the bottom silicon dioxide layer
22
is of particular importance to the subject matter of the present invention.
Referring now to
FIG. 2
, the processing steps used in the prior art to create the non-volatile memory cell are illustrated. The tunneling oxide layer
14
is formed overlying the semiconductor substrate
10
and STI regions
12
. A first polysilicon layer
18
is then deposited overlying the tunneling oxide layer
14
. The first polysilicon layer
18
and the tunneling oxide layer
14
are patterned to form the floating gate for the device.
Referring now to
FIG. 3
, the first layer of the interpoly dielectric is formed. A bottom silicon dioxide layer
22
is grown overlying the floating gate
18
and the STI
12
. A thermal oxidation process is used to grow the bottom silicon dioxide layer
22
overlying the polysilicon and silicon material of the floating gate
18
and STI
12
, respectively. A problem in the prior art is shown by the formation of a wavy topology
35
in the bottom silicon dioxide layer
22
. The wavy topology
35
is due to the rapid and uneven oxidation rate of the polysilicon material of the floating gate
22
.
The wavy topology
35
of the prior art process causes charge leakage over the completed O—N—O dielectric and leads to data retention problems. In addition, the rapid and uneven oxidation rate of the polysilicon material makes it difficult to scale down or reduce the thickness of the bottom silicon oxide layer
22
. This fact limits the viability of the O—N—O stack in smaller geometry devices.
Several prior art approaches disclose methods to form non-volatile memories and to form dielectric layers. U.S. Pat. No. 5,847,427 to Hagiwara discloses a process to form a non-volatile memory device. An oxidation suppressing layer is formed in an upper surface of the floating gate after the floating gate is defined. The interpoly dielectric (O—N—O) layer is then deposited by a chemical vapor deposition. The oxidation suppressing layer is used to eliminate bird's beak formation on the floating gate during an isolation thermal oxidation that is performed after the interpoly dielectric and control gate are formed. U.S. Pat. No. 5,422,291 to Clementi et al teaches an alternative dielectric for non-volatile memory cells. The O—N—O stack between the floating gate and the control gate is replaced with an RTN-N—O stack. Rapid thermal nitridation (RTN) is used to form a nitridized skin over the floating gate. The RTN process is performed by thermal diffusion. A silicon nitride layer is then deposited. Finally, a thermal oxide is grown. U.S. Pat. No. 5,567,638 to Lin et al discloses a process to form polysilicon resistors. A first polysilicon layer, which may form transistor gates, is exposed to a thermal nitridation process to form a nitridized surface layer. A second polysilicon, from which resistors will be formed, is then deposited. Boron is implanted into the second polysilicon to increase resistivity. The presence of the nitridized layer over the first polysilicon prevents boron diffusion from the second polysilicon. U.S. Pat. No. 5,661,056 to Takeuchi teaches a method to form non-volatile memory cells. The O—N—O dielectric between the floating gate and the control gate is replaced with an N—O—N stack. The first silicon nitride layer overlying the floating gate may be formed by RTN.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to form non-volatile memory cells in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to improve the smoothness of the bottom silicon dioxide layer of the O—N—O stack by implanting nitrogen into the floating gate polysilicon layer prior to thermal oxidation.
A yet further object of the present invention is to improve the data retention capability of the non-volatile memory cell.
Another yet further object of the present invention is to allow the thickness of the bottom silicon dioxide layer of the O—N—O stack to be reduced.
In accordance with the objects of this invention, a new method of forming non-volatile memory cells with an improved bottom silicon dioxide layer of the O—N—O stack in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A tunneling dielectric layer is grown overlying the semiconductor substrate. A polysilicon layer is deposited overlying the tunneling dielectric layer. Ions may be implanted into the polysilicon layer to alter resistivity. Nitrogen is implanted into the polysilicon layer to form a nitridized surface region. The polysilicon layer and the tunneling dielectric layer are then patterned to form floating gates. A bottom silicon dioxide layer is grown overlying the floating gates by thermal oxidation of the polysilicon layer. The nitridized surface region reduces the rate of thermal oxidation and creates a smooth surface.
A silicon nitride layer is deposited overlying the bottom silicon dioxide layer. A top silicon dioxide layer is deposited overlying the silicon nitride layer to complete the O—N—O stack. A conductive layer, that may comprise polysilicon, is deposited overlying the top silicon dioxide layer. The conductive layer, the top silicon dioxide layer, the silicon nitride layer, and the bottom silicon dioxide layer are patterned to form control gates and to complete the non-volatile memory cells in the manufacture of the integrated circuit device.


REFERENCES:
patent: 5422291 (1995-06-01), Clementi et al.
patent: 5567638 (1996-10-01), Lin et al.
patent: 5661056 (1997-08-01), Takeuchi
patent: 5972751 (1998-08-01), Ramsbey et al.
patent: 5847427 (1998-12-01), Hagiwara
patent: 6127227 (1999-01-01), Lin et al.

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