Method to form high performance copper damascene...

Details Method to form high performance copper damascene... Method to form high performance copper damascene...

2000-10-02

2002-04-30

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S637000, C438S672000, C438S675000

Reexamination Certificate

active

06380084

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of dual damascene copper interconnects in the manufacture of integrated circuit devices.
2. Description of the Prior Art
Copper damascene interconnects are becoming increasingly common in the art of integrated circuit manufacture. Copper interconnects offer a significant advantage over aluminum interconnects because of the lower resistivity of copper. In copper damascene processes, trenches are patterned into a dielectric material. Copper is then blanket deposited overlying the dielectric material to fill the trenches. Finally, a polish down operation is performed to remove excess copper and to form the interconnect patterns within the confines of the trenches.
Referring to
FIG. 1
, a cross-section of a partially completed dual damascene structure in a prior art integrated circuit device is shown. In this interconnect structure, a level of connective lines will be formed overlying a conductive layer
18
. Vias will also be formed to selectively connect the level of connective lines to the underlying conductive layer
18
. An insulator layer
14
overlies a semiconductor substrate
10
. The conductive layer
18
overlies the insulator layer
14
. A first etch stopping layer
20
is formed overlying the conductive layer
18
. A first dielectric layer
22
is formed overlying the first etch stopping layer
18
. A second etch stopping, layer
26
, typically comprising silicon nitride, overlies the first dielectric layer
22
. A second dielectric layer
30
overlies the etch stopping layer
26
. The second dielectric layer
30
is patterned to form an upper trench that may be called the connective line trench. Note that the presence of the second etch stopping layer
26
facilitates etching the second dielectric layer
30
to specific depth.
Referring now to
FIG. 2
, the etch stop layer
26
and the first dielectric layer
22
are patterned to form the lower trench, that is called the via trench. The first etch stopping layer
20
is then etched through to expose the underlying conductive layer
18
.
Referring now to
FIG. 3
, a barrier layer
32
and a copper layer
34
are deposited and polished down to complete the dual damascene interconnect structure.
There are two significant problems in the prior art method. First, the first and second silicon nitride etch stopping layers
20
and
26
significantly increases the parasitic capacitance of the interconnect structure. Second, the copper layer
34
is deposited in both the via and connective line trenches in one process. Unfortunately, it is difficult to control the deposition rate of the copper layer
34
in both the high aspect ratio via trench and in the lower aspect ratio connective line trench. The properties of the copper layer
34
are thereby chronically degraded. Deposited copper grain sizes and texture change with the aspect ratio and the sidewall features. Therefore, the properties of the copper in the via are different from the properties of the copper in the trench. This is an important point that has been ignored until now. Poor copper layer filling, due to differences in the aspect ratios of the trench and via, reduces the interconnect performance in the completed integrated circuit device.
Several prior art approaches disclose methods to form dual damascene structures in the fabrication of integrated circuits. U.S. Pat. No. 6,040,243 to Li et al discloses a method to form dual damascene interconnects. Via and connective line trenches are filled in one copper deposition step. Barrier layer sidewall spacers on the trenches are used to prevent copper diffusion into the dielectric material during etching. U.S. Pat. No. 5,741,626 to Jain et al teaches a method to form dual damascene interconnects using tantalum nitride layers. Via and connective line trenches are filled in one copper deposition step. U.S. Pat. No. 5,981,374 to Dalal et al discloses a multi-level interconnect structure where adjoining insulating layers comprise differing material types to eliminate metal spiking. U.S. Pat. No. 5,933,761 to Lee teaches a method to form dual damascene structures. Nitrogen is implanted into the dielectric layer to create a buried etch stop layer. U.S. Pat. No. 5,930,669 to Uzoh discloses a method to form damascene interconnect structures. A trench liner layer is sputter deposited so that copper is left exposed at the trench bottom. After filling the trench with copper, an anneal is performed to crystallize adjoining copper layers and thereby improve conductivity.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming dual damascene copper interconnects in the manufacture of an integrated circuit device.
A further object of the present invention is to provide a method to fabricate dual damascene copper interconnects where the connective line and via trenches are filled in separate copper depositions to thereby improve performance.
Another further object of the present invention is to remove all unnecessary capping layers to thereby reduce the inter-layer capacitance.
Another further object of the present invention is to provide a method to fabricate dual damascene copper interconnects wherein the silicon nitride etch stop layer is eliminated to thereby reduce interconnect capacitance.
Another further object of the present invention is to provide a method of forming dual damascene interconnects whereby the first copper layer of the vias can be used as a seed layer for the subsequent deposition of a second copper layer into the upper interconnect trenches.
Another further object of the present invention is to provide a method to fabricate a robust copper line and via structure that is compatible with current electroless plating and electroplating processes and future deposition technologies.
In accordance with the objects of this invention, a method to form robust dual damascene interconnects by de-coupling via and connective line trench filling in the manufacture of an integrated circuit device has been achieved. A conductive layer is provided overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the conductive layer. A first dielectric layer is deposited overlying the conductive layer. A shielding layer is deposited overlying the first dielectric layer. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches that expose a part of the conductive layer. A first barrier layer is deposited overlying the conductive layer and lining the via trenches. The via trenches are filled with a first copper layer. This filling may comprise a single deposition of copper or a first deposition of a seed layer followed by electroless or electrochemical plating of the first copper layer. The first copper layer and the first barrier layer are polished down to complete the vias. A second barrier layer is deposited overlying the first dielectric layer and the vias. The second barrier layer is patterned to form via caps overlying the vias. Alternatively, the first copper layer may be recessed below the top of the via trenches. The second barrier layer is deposited and then polished down to form via caps. A second dielectric layer is deposited overlying the via caps and the first dielectric layer. A capping layer is deposited overlying the second dielectric layer. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited overlying the via caps and lining the connective line trenches. The third barrier layer and the via caps are anisotropically etched down to form barrier sidewall spacers lining the connective line trenches and to expose a part of the first copper layer. The connective line trenches are filled with a second copper layer. This filling may comprise a single deposition of copper, a first dep

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