Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-02
2005-08-02
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S297000, C438S257000
Reexamination Certificate
active
06924199
ABSTRACT:
A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the substrate with a dielectric layer therebetween. A masking layer is formed overlying the conductor layer. A resist layer is formed overlying the masking layer. The resist layer is patterned to thereby selectively expose the masking layer. The resist layer exhibits a first spacing between edges of the resist layer. The exposed masking layer is etched through to thereby selectively expose the conductor layer. The etched edges of the masking layer are tapered such that the masking layer exhibits a second spacing between the masking layer edges at the top surface of the conductor layer. The second spacing is less than the first spacing. The exposed conductor layer is etched through to thereby complete a transistor gate.
REFERENCES:
patent: 5893757 (1999-04-01), Su et al.
patent: 6060375 (2000-05-01), Owyang et al.
patent: 6177331 (2001-01-01), Koga
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6342451 (2002-01-01), Ahn
patent: 6514868 (2003-02-01), Hui et al.
patent: 6544838 (2003-04-01), Ranade et al.
patent: 6649473 (2003-11-01), Lin et al.
patent: 6673676 (2004-01-01), Lin et al.
patent: 6677224 (2004-01-01), Tseng
patent: 6740550 (2004-05-01), Choi et al.
patent: 6777342 (2004-08-01), Hwang
patent: 6812095 (2004-11-01), Taylor
patent: 6818459 (2004-11-01), Wack et al.
Chu Wen-Ting
Liu Shih-Chang
Lebentritt Michael
Lindsay Jr. Walter L.
Taiwan Semiconductor Manufacturing Co. Ltd.
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