Method to form capacitance node contacts with improved isolation

Details Method to form capacitance node contacts with improved isolation Method to form capacitance node contacts with improved isolation

1999-02-25

2000-02-01

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 218242

Patent

active

06020236&

ABSTRACT:
A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilicon plug are polished to a planar surface. A first interpoly isolation layer is deposited. A stopping layer is deposited. A capping layer is deposited. A first polysilicon layer is deposited. The first polysilicon layer is etched to form features. A second interpoly isolation layer is deposited. The second interpoly isolation layer is planarized. The second contact hole is etched through the second interpoly isolation layer and the capping layer. The exposed first polysilicon material is etched back to the vertical sides of the second contact hole. The stopping layer and the first interpoly isolation layer are etched through to the top surface of the polysilicon plug. A lining layer of silicon nitride is deposited and etched to remain only on the vertical interior surfaces of the second contact hole. A second polysilicon layer is deposited to fill the second contact hole. The second polysilicon layer and the second interpoly isolation layer are planarized. The fabrication of the integrated circuit device is completed.

REFERENCES:
patent: 5545584 (1996-08-01), Wuu et al.
patent: 5763306 (1998-06-01), Tsai
patent: 5770498 (1998-06-01), Becker
patent: 5789291 (1998-08-01), Sung
patent: 5981333 (1999-11-01), Parekh et al.

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