Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-10-25
2001-06-26
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S758000, C438S411000
Reexamination Certificate
active
06252290
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to multilevel interconnects employed in semiconductor devices, and more specifically to increasing the speed of damascene interconnects in semiconductor devices.
BACKGROUND OF THE INVENTION
Although air gap design for interconnects in semiconductor devices having low-k (dielectric constant) and good RC time constant by replacing the interlayer silicon dioxide (dielectric constant k of about 4) with air (dielectric constant k of about 1), support is lacking on the via stack and metal line. This limits the number of metal layer interconnects that may be fabricated.
U.S. Pat. No. 5,559,055 to Chang et al. describes a method of decreasing the RC time constant by reducing the capacitance C by replacing the interlayer silicon dioxide (k=4) with air (k=1). Alternatively, the air space can also be filled with another low dielectric constant material in the range of about 2.2 to 3.4. In either case, the final effective dielectric constant of the device is lowered, thus lowering the RC time constant resulting in higher device speed.
U.S. Pat. No. 5,708,303 to Jeng describes a device and method of optimizing capacitance and performance for multilevel, damascene interconnects that may have air gaps between closely spaced metal interconnects. Crosstalk voltage is reduced by including a dielectric material having a higher permitivity between two metal layers to increase interlayer capacitance and inserting a low-dielectric constant material between metal lines.
U.S. Pat. No. 5,891,797 to Farrar describes a process of manufacturing integrated circuits for designing and implementing a hierarchical wiring system with the interconnection requirements sorted and designed into a particular wiring level according to length. Support structures, such as lateral ribs or intermediate posts fabricated of either insulating or conductive material, may be constructed to allow more flexibility in designing air bridge dimensions.
U.S. Pat. No. 5,882,963 to Kerber et al. describes a method of manufacturing a semiconductor component having capacitances occurring between contacts, interconnects, or metallizations reduced by filling cavities with air or gas. The cavities are produced between the semiconductor material and a passivation layer in a region wherein the interconnects are surrounded by dielectric and are subsequently closed by a further passivation layer.
U.S. Pat. No. 5,324,683 to Fitch et al. describes a method for forming an air region or an air bridge overlying a base layer to: provide for improved dielectric isolation of adjacent conductive layers; provide air-isolated conductive interconnects; and/or form many other microstructures or microdevices.
U.S. Pat. No.
5
,
548
,
099
to Cole, Jr. et al. describes a method for preserving an air bridge structure on an integrated circuit chip without sacrificing metallization routing area in an overlying high density interconnect structure. A protective layer is sublimed over the air bridge to provide mechanical strength while preventing contamination and deformation during processing.
U.S. Pat. No. 5,670,828 to Cheung et al. describes a semiconductor device with its control speed increased by forming air tunnels in the interwiring spaces of a conductive pattern to reduce intra-conductive layer capacitance.
U.S. Pat. No. 5,413,962 to Lur et al. describes a method of formation of a multilevel electrode metal structure and the interconnecting interlevel metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed, the interlevel dielectric material used in forming the structure is etched away leaving air dielectric between the levels.
U.S. Pat. No. 5,900,668 to Wollesen describes a semiconductor device having reduced parasitic capacitance, and thus increased integrated circuit speed, by removing sections of dielectric interlayers which do not support conductive patterns to form air gaps which may be filled in with a dielectric material having a low dielectric constant.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming a dual damascene multilevel interconnect semiconductor device having air gaps between the inter- and intra-level metal lines to achieve a low RC time constant.
Another object of the present invention is to provide a method of forming a dual damascene multilevel interconnect semiconductor device utilizing air gaps to reduce the RC time constant and having polymer support under the metal line and adjacent the via stack permitting increased interconnect levels.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains. Air gaps are adjacent the at least one interconnect structure and are formed within the interlevel and intralevel layers.
REFERENCES:
patent: 3890636 (1975-06-01), Harada et al.
patent: 5117278 (1992-05-01), Thomas et al.
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5413962 (1995-05-01), Lur et al.
patent: 5548099 (1996-08-01), Cole, Jr. et al.
patent: 5559055 (1996-09-01), Chang et al.
patent: 5670828 (1997-09-01), Cheung et al.
patent: 5708303 (1998-01-01), Jeng
patent: 5828121 (1998-10-01), Lur et al.
patent: 5882963 (1999-03-01), Kerber et al.
patent: 5891797 (1999-04-01), Farrar
patent: 5900668 (1999-05-01), Wollesen
patent: 6078088 (2000-06-01), Buynoski
patent: 6143641 (2000-11-01), Kitch
patent: 6184121 (2001-02-01), Buchwalter et al.
Ang Ting Cheong
Chan Lap
Loong Sang Yee
Quek Shyue Fong
Chartered Semiconductor Manufacturing Ltd.
Clark Sheila V.
Pike Rosemary L. S.
Saile George O.
Stanton Stephen G.
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