Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-16
2001-10-23
Bowers, Charles (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06306714
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices, and more particularly to the fabrication of an elevated contact to doped regions in a CMOS device.
2) Description of the Prior Art
The semiconductor industry has been advanced in an ever brisk pace, recently. In order to achieve high performance integrated circuits or high package density of a wafer, the sizes of semiconductor devices have become smaller and smaller than before in the field of Ultra Large Scale Integrated (ULSI) technologies.
Integrated circuits includes more than millions of devices in a specific area of a wafer and electrically connecting structure for connecting these devices to perform desired function. One of the typical devices is metal oxide semiconductor field effect transistor (MOSFET). The MOSFET has been widely, traditionally applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues to fabricate them. The typically issue that relates to hot carriers injection is overcame by the development of lightly doped drain (LDD) structure.
As transistors are scaled down even further, short channel effect (SCE) are severe. There is a challenge to make elevated source/drain (S/D) to reduce the short channel effect (SCE).
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,804,846 (Fuller) that teaches a method for a self aligned elevated S/D by W layer and chemical-mechanical polish.
U.S. Pat. No. 5,422,289 (Pierce) shows elevated source/drain (S/D) formed by chemical-mechanical polish (CMP) a poly layer.
U.S. Pat. No. 6,015,727 (Wanlass) teaches a damascene source/drain (S/D) process.
U.S. Pat. No. 5,851,883 (Gardner et al.) shows a chemical-mechanical polish (CMP) gate and S/D process.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a MOS device with improved short channel effect (SCE).
It is an object of the present invention to provide a method for fabricating a MOS transistor with an elevated source/drain (S/D).
It is an object of the present invention to provide a method for fabricating a MOS transistor with an elevated source/drain (S/D) and a metal plug contact through the elevated S/D to the doped source/drain (S/D) in the substrate.
It is an object of the present invention to provide a method for fabricating a MOS transistor a first and second lightly doped drains, with an elevated source/drain (S/D) and a metal plug contact through the elevated S/D to the doped source/drain (S/D) in the substrate.
To accomplish the above objectives, the present invention provides a method of fabrication of an elevated source/drain (S/D) for a MOS device can be summarized as follows. A first insulating layer is formed over a substrate. A gate opening and source/drain openings are created in the first insulating layer exposing the substrate. The first insulating layer between the gate opening and the source/drain (S/D) openings are spacer blocks. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. We implant ions through the source/drain openings to form first lightly doped drain regions in the substrate. Then we remove the LDD resist mask. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. We form a gate in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. We form plug opening through the raised source/drain (S/D) blocks. We form contact plugs in the form plug opening.
The invention's first and second LDD, contact plugs and elevated S/D regions reduce the short channel effect (SCE). Key features of the invention are the:
elevated source/drain (S/D) blocks,
the first and second LDD, and
the plug contact.
The invention reduces SCE because the N+/{+ drain is formed by a diffusing of (n+) dopant from the poly layer. The junction can be extremely shallow. TiSix or CoSix can be formed on top of the poly layers without causing any junction leakage.
In addition, the invention provide a method that is very manufacturable and uses planarization processes to control thicknesses.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5422289 (1995-06-01), Pierce
patent: 5804846 (1998-09-01), Fuller
patent: 5851883 (1998-12-01), Gardner et al.
patent: 6015727 (2000-01-01), Wanlass
patent: 6140191 (2000-10-01), Gardner et al.
patent: 6140224 (2000-10-01), Lin
patent: 6245603 (2001-06-01), Shinohara
Chan Lap
Lee James Yongmeng
Leung Ying Keung
Pan Yang
Pradeep Yelehanka Ramachandramurthy
Bowers Charles
Chartered Semiconductor Manufacturing Inc.
Pike Rosemary L. S.
Roman Angel
Saile George O.
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