Method to form a vertical transistor by first forming a...

Details Method to form a vertical transistor by first forming a... Method to form a vertical transistor by first forming a...

2002-01-03

2003-04-08

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S192000, C438S206000, C438S212000

Reexamination Certificate

active

06544824

ABSTRACT:

BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device, and more particularly to the fabrication of a MOS transistor with a vertical channel.
2) Description of the Prior Art
Field effect transistors (FET's) are a fundamental building block in the field of integrated circuits. FET's can be classified into two basic structural types: horizontal and vertical. Horizontal, or lateral, FET's exhibit carrier flow from source to drain in a direction parallel (e.g. horizontal) to the plane of the substrate on which they are formed. Vertical FET's exhibit carrier flow from source to drain in a direction transverse to the plane of the substrate (e.g. vertical) on which they are formed.
While horizontal FET's are widely used and favored in the semiconductor industry because they lend themselves easily to integration, vertical FET's have a number of advantages over horizontal FET's. Because channel length for vertical FET's is not a function of the smallest feature size resolvable by state-of-the-art lithographic equipment and methods (e.g. on the order of 0.25 micrometers), vertical FET's can be made with a shorter channel length (e.g. on the order of 0.1 micrometers) than horizontal FET's, thus providing vertical FET's the capability to switch faster and as well as a higher power handling capacity than horizontal FET's. There is also the potential for greater packing density with vertical FET's.
The importance of overcoming the various deficiencies note above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,414,289 (Fitch et al.) that shows one vertical transistor that is formed by form gate/spacer stack, etch and then SEG for S/D and channel.
U.S. Pat. No. 5,398,200 (Mazure et al.) describes a two vertical memory transistor cell using epi growth.
U.S. Pat. No. 5,218,218 (Akazawa) shows a vertical Transistor in a trench. Akazawa forms the S/D & channel by diffusion.
U.S. Pat. No. 5,780,327 (Chu et al.) shows a vertical double gate transistor.
U.S. Pat. No. 5,545,586 (Koh) shows a vertical transistor using epi layers.
U.S. Pat. No. 5,340,759 (Hsieh et al.) shows a vertical gate transistor using epi.
U.S. Pat. No. 5,032,529 (Beitman et al.) shows a trench gate VCMOS transistor.
U.S. Pat. No. 4,982,266 (Chjatterjee) and U.S. Pat. No. 5,302,5412 (Akazawa) show other transistor processes.
SUMMARY OF THE INVENTION
It is an object of a preferred embodiment of the present invention to provide a method for fabricating a vertical transistor.
It is an object of a preferred embodiment of the present invention to provide a structure and method for fabricating a vertical transistor by first forming gate/spacer stack, then using selective epitaxy to form source/drain and channel.
The objectives do not limit the scope of the invention in any way.
To accomplish the above objectives, the present invention provides a method of manufacturing a vertical transistor.
A doped region is formed in a substrate. We form sequentially on the substrate, a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. We form a masking layer having an opening over the third spacer dielectric layer. We form a trench through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. We form a gate dielectric layer over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. We form a cap layer over the structure. Contacts are formed to the doped region, the first gate electrode the second doped layer, third doped layer and the fourth doped layer.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.


REFERENCES:
patent: 4788158 (1988-11-01), Chatterjee
patent: 4982266 (1991-01-01), Chatterjee
patent: 5032529 (1991-07-01), Beitman et al.
patent: 5218218 (1993-06-01), Akazawa
patent: 5302541 (1994-04-01), Akazawa
patent: 5340754 (1994-08-01), Witek et al.
patent: 5340759 (1994-08-01), Hsieh et al.
patent: 5398200 (1995-03-01), Mazuré et al.
patent: 5414289 (1995-05-01), Fitch et al.
patent: 5545586 (1996-08-01), Koh
patent: 5780327 (1998-07-01), Chu et al.
patent: 6372559 (2002-04-01), Crowder et al.
patent: 6461900 (2002-10-01), Sundaresan et al.

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