Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-13
2001-10-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S291000, C438S300000
Reexamination Certificate
active
06300201
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to improve the density and performance of a metal oxide semiconductor field effect transistor, (MOSFET), device, via use of enhanced processes and non-conventional gate materials.
(2) Description of Prior Art
The advent of micro-miniaturization, or use of sub-micron features, for the fabrication of MOSFET devices, is dependent on the ability of the semiconductor industry to develop new processes, and new materials, to allow the fabrication of sub-micron MOSFET devices to be realized. The attainment of sub-micron features, of 1000 Angstroms or less, realized via advancements in several semiconductor fabrication disciplines, such as photolithography, and reactive ion etching, (RIE), are benefitted by the use of dielectric layers exhibiting higher dielectric constants than the conventionally used silicon dioxide, as well as benefitted by the use of metal gate structures, with lower resistance than the conventionally used polysilicon gate structure. The need for thinner layers and structures, for use in sub-micron MOSFET devices, make the use of the high k gate insulator layer, and the metal gate structure imperative. However the high k insulator layers can not withstand temperatures greater than about 500° C. Specific process sequences, conventionally performed after gate insulator formation can degrade the integrity of the high k gate insulator layer.
This invention will describe a process sequence that allows the narrow, and shallow dopant profiles of anti-punchthrough, and of source/drain regions, to be obtained, and then retained via self-aligned processes, performed prior to the formation of the high k gate insulator layer. In addition the spacer sidewall procedure, is performed prior to the formation of the narrow anti-punchthrough region, thus preserving the desired narrow profile of this region. This is accomplished via use of a dummy gate structure, used to provide a structure for accommodation of the sidewall spacers. After formation of the source/drain region, and removal of the dummy gate structure, the anti-punchthrough region is formed in the region of the semiconductor substrate which previously was occupied by the dummy gate structure. A high k gate insulator layer is then formed on the surface vacated by the dummy gate structure, followed by the formation of a metal gate structure, overlying the high k gate insulator layer, in the space vacated by the dummy gate structure, butting against the previously formed spacer sidewalls. Prior art, such as Lee et al, in U.S. Pat. No. 5.656,225, as well as Kao et al, in U.S. Pat. No. 5,688,700, describe processes for enhancing MOSFET devices, in terms of narrow and shallow dopant regions, as well as the use of dummy gate structures, however none of these prior arts describe the use of a high k gate insulator layer, and an overlying metal gate structure, formed after the self-aligned creation of narrow, and shallow dopant regions.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a MOSFET device using a high k, gate insulator layer, and a metal gate structure.
It is another object of this invention to restrict the exposure of the high k, gate insulator layer, and the metal gate structure, to subsequent process temperatures greater than 500° C., therefore forming the high k, gate insulator layer after the formation of gate structure sidewall spacers, and after formation of source/drain region.
It is still another object of this invention to self-align the source/drain region, using a dummy gate structure as a defining shape, followed by removal of the dummy gate structure, and implantation of channel implant regions, self-aligned in the space vacated by the dummy gate structure.
In accordance with the present invention a method of fabricating a MOSFET device structure, featuring a high k, gate insulator layer, and a metal gate structure, created after formation of sidewall spacers, and after formation of source/drain regions, both requiring process temperatures that would degrade the high k gate insulator layer, is described. After formation of well regions, and of isolation regions, a dummy, or disposable silicon nitride gate structure, is formed on an underlying silicon oxide pad layer. After formation of a lightly doped source/drain region, using the dummy gate structure as a mask, silicon oxide spacers are formed on the sides of the dummy gate structure, followed by formation of a heavily doped source/drain region, using the dummy gate structure, and the spacers, on the sides of the dummy gate structure, as a mask. Metal silicide layers are then formed on the surface of the exposed heavily doped source/drain region, followed by the deposition, and planarization of an interlevel dielectric layer. After selective removal of the dummy gate structure, resulting in an opening exposing the semiconductor channel region, ion implantation procedures are performed to self-align threshold adjust, and anti-punchthrough regions, in the channel region of the semiconductor substrate. After removal of the silicon oxide pad layer, a high k, gate insulator layer is deposited on the top surface of the semiconductor channel region. Deposition of a metal layer, followed by removal of unwanted regions of the metal layer, from the top surface of the interlevel dielectric layer, result in the formation of a metal gate structure, overlying the high k, gate structure, in the opening created by the removal of the dummy gate structure.
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Chu Sanford Shao Fu
Shao Kai
Wang Yi Min
Zhang Jiong
Zhang Qing Hua
Chartered Semiconductor Manufacturing Ltd.
Lindsay Jr. Walter L.
Niebling John F.
Pike Rosemary L. S.
Saile George O.
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