Method to fabricate RF inductors with minimum area

Details Method to fabricate RF inductors with minimum area Method to fabricate RF inductors with minimum area

2001-05-31

2002-05-14

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S381000, C438S687000

Reexamination Certificate

active

06387747

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of integrated microelectronic circuitry having passive circuit components formed therein, more specifically to such a circuit having an inductor formed therein.
2. Description of the Related Art
It is well known that fabricating microelectronics circuitry, wherein active and passive components are monolthically integrated, is advantageous both from the standpoint of reducing manufacturing costs and from the standpoint of producing a circuit with improved operating characteristics. When considering methods of forming such passive components, however, inductors pose more challenges than either resistors or capacitors. For the purposes that they are required, microelectronic inductors must have both a high inductance (eg. to reduce power consumption) and high quality factor (Q factor.) Quality factor is defined as the ratio of energy stored to energy dissipated (Es/Ed) by a device, which can be shown to be equal to Im(Z)/Re(Z), the ratio of the imaginary part of the impedance, Z, and its real part. Generally, the imaginary part, Im(Z), is the reactance of the device, which, for a device having both capacitative as well as inductive characteristics is given by the difference between the inductive reactance and the capacitative reactance at the frequency of operation, &OHgr;:
Im
(
Z
)=&ohgr;
L
−1
/&ohgr;C.
The real part, Re(Z), is determined by the sum of the inductor's resistive losses, which we can simply call R. Thus:
Q
=(&ohgr;
L
−1
/&ohgr;C
)/
R.
For an inductor with little or no capacitative component, the Q is simply &ohgr;L/R.
When the inductor is formed as a monolithic structure within a larger integrated fabrication, the capacitance and resistive parts include effects due to coupling between the inductor and its surroundings, ie. parasitic effects. Burghartz et al. (U.S. Pat. No. 6,054,329) discloses a damascened spiral and toroidal inductor wherein the spiral inductor is planar and the toroidal inductor is spirally formed around a ferromagnetic core. Dow et al. (U.S. Pat. No. 5,478,773) provides a plated copper integrated planar spiral inductor, wherein the inductor is contained within a square area of 410 microns on a side and has an inductance of 50 nH (nanoHenries) and a Q factor of 15 or greater. Yu et al. (U.S. Pat. No. 5,793,096) discloses an inductor device with MOS transistors installed therein. Lowther (U.S. Pat. No. 5,717,243) discloses a spiral inductor that is formed over a semiconductor device substrate. The Q value of the inductor is increased by a formation wherein circumferential parasitic currents are channeled through doped regions of the substrate, reducing its resistance and lowering the real part of its impedance. Abidi et al. (U.S. Pat. No. 5,539,241) provides an integrated circuit with an energy storing inductor which is monolithically formed within an oxide layer overlaying a silicon substrate. To reduce parasitic capacitances, an opening is formed within the silicon substrate beneath the inductor and filled with an insulating material to effectively isolate the inductor.
Conventional planar inductors suffer from several disadvantages which adversely affect both their inductance and their Q factor. To provide a high inductance, they must have a large number of windings and a cover a correspondingly large area. This, however, produces sizeable parasitic capacitances as well as increased energy dissipation within the underlying substrate. In order to increase Q while not reducing L requires an inductor that covers a smaller area for a given number of windings. In addition, a planar spiral produces much of its magnetic field within the substrate, which induces oppositely directed fields that reduce the inductance of the coil. On the other hand, a helical or solenoidal shaped inductor confines more of its magnetic field within the coil formation, thus improving its inductive characteristics. For this reason, a helical inductor occupying a small area would be an optimal formation for an inductor with large L and high Q.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming, within a minimum area of an integrated microelectronics fabrication, an RF inductor having a large inductance and high quality factor.
It is a further object of the present invention to provide a method for forming such an inductor wherein there is minimal capacitative coupling and significantly reduced cross-talk between adjacent levels of metallization such as that associated with coils and interconnects.
It is yet a further object of the present invention to provide a method for forming such a minimum area RF inductor in a manner that does not involve the etching of formations with high aspect ratios.
It is yet a further object of the present invention to provide a method for forming such a minimum area RF inductor in a manner that is easily and efficiently implemented within current fabrication processes for microelectronics circuitry.
It is yet a further object of the present invention to provide a coil structure having large inductance and high quality factor together with increased versatility of circuit placement and a corresponding broader range of applicability within the constraints of circuit design.
The above objects of the present invention will be realized by a method of forming a helical RF inductor with metal or copper damascene coils that alternate in width from wide to narrow, wherein more coils can be formed and accommodated within the same area as a helical inductor with coils of uniform width fabricated according to the prior art. Said method is easily accomplished by strategically allocating metals within different intermetal dielectric (IMD) levels of an integrated microelectronics fabrication.


REFERENCES:
patent: 5478773 (1995-12-01), Dow et al.
patent: 5539241 (1996-07-01), Abidi et al.
patent: 5717243 (1998-02-01), Lowther
patent: 5793096 (1998-08-01), Yu et al.
patent: 6054329 (2000-04-01), Burghartz et al.
patent: 6187647 (2001-02-01), Chu
patent: 6309922 (2001-10-01), Liu et al.

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