Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-12
2003-12-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S303000, C438S301000
Reexamination Certificate
active
06660605
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to methods for forming transistor source/drain regions having a sharp HDD portion buried within a graded HDD portion in the fabrication of semiconductor devices.
BACKGROUND OF THE INVENTION
MOS transistors are found in many modern semiconductor products where switching and/or amplification functions are needed. Many manufacturing processes and techniques have been developed for fabricating MOS devices in semiconductor substrate materials such as silicon and the like. In recent years, the size of transistors and other components have steadily decreased to submicron levels in order to facilitate higher device densities in semiconductor products. At the same time, many new applications have created a need to operate transistors and other semiconductor devices at lower power and voltage levels. Thus, whereas previous MOSFET devices were designed to operate at voltages of 5 or more volts, newer applications may require such devices to operate from DC supplies of around 3 volts or less. In addition, switching speed requirements of MOS transistors continue to increase in order to facilitate faster and improved product performance. Accordingly, efforts continue to be made to design semiconductor devices, such as MOSFET transistors, which occupy less physical space, consume less power, and operate at higher switching speeds and at lower voltages.
MOS transistors include a conductive gate overlying a channel region of the substrate with a thin gate dielectric, typically oxide, therebetween. Source and drain regions of the substrate (sometimes referred to as junction regions) are doped with impurities on opposite sides of the channel, wherein the source/drain regions of NMOS devices are doped with n-type impurities (e.g., As, Sb, P, etc.) and PMOS devices are doped using p-type impurities (e.g., B, Ga, In, etc.). The length of the gate structure overlying the channel typically dictates the physical channel length thereunder. The source and drain dopants are typically implanted into the silicon substrate using ion implantation systems, wherein the dosage and energy of the implanted ions may be varied depending upon the desired dopant concentration, depth, and profile. The ion dosage generally controls the concentration of implanted ions for a given semiconductor material, and the energy level of the ions determines the distance of penetration or depth of the implanted ions (e.g., the junction depth).
One specific type of implant is the “quad high-angle implant” (QHA), which may be performed on the MOS device, wherein four separate high angle implants are done on the device wafer. Each implant is typically performed on the wafer held in a position, then rotationally indexed by 90 degrees.
Following implantation, the dopant atoms in the source/drain regions occupy interstitial positions in the substrate lattice, and the dopant atoms must be transferred to substitutional sites to become electrically active. This process is sometimes referred to as “activation”, and is accomplished by high temperature annealing in an inert ambient such as argon. The activation anneal process also causes diffusion of implanted dopant species downward and laterally in the substrate, wherein the effective channel length becomes less than the gate width. As device sizes continue to shrink, the channel lengths continue to be scaled downward, wherein short channel effects become significant.
In addition to short channel effects, hot carrier effects are also experienced in short channel devices. For example, during saturation operation of a MOS transistor, electric fields are established near the lateral junction of the drain and channel regions. This field causes channel electrons to gain kinetic energy and become “hot”. Some of these hot electrons traveling to the drain are injected into the thin gate dielectric proximate the drain junction. The injected hot carriers, in turn, often lead to undesired degradation of the MOS device operating parameters, such as a shift in threshold voltage, changed transconductance, changed drive current/drain current exchange, and device instability.
To combat channel hot carrier effects, drain extension regions are commonly formed in the substrate, which are variously referred to as double diffused drains (DDD), lightly doped drains (LDD), and moderately doped drains (MDD). These drain extension regions absorb some of the potential into the drain and away from the drain/channel interface, thereby reducing channel hot carriers and the adverse performance degradation associated therewith.
The success of the MOS transistor has been partially due to the capability of the MOS transistor to take advantage of the lateral scaling improvements in the technologies. Lateral scaling results in simultaneous improvements in both the performance and the packing density of the devices. Although generalized scaling has served well for the last few decades, many of the technology advances that allow the devices to continue improving the performance and the packing density are approaching fundamental physical limitations.
Gate oxide thickness, junction scaling, and well engineering in MOS devices has enabled channel length scaling by improving short channel characteristics. By changing the doping profile in the channel region, the distribution of the electric field and potential contours can be changed. The goal is to optimize the channel profile to minimize the off-state leakage while maximizing the linear and saturation drive currents. Channel doping optimization can improve the circuit gate delay, for example, by about 10% for a given technology. Super Steep Retrograde Wells (SSRW) and halo implants (or pocket implants) have been used as a means to scale the channel length and increase the transistor drive current without causing an increase in the off-state leakage current.
The halo architecture creates a localized 2-D graded dopant distribution near the source/drain (S/D) regions and extends under the channel. Halos are generally known for their ability to stop unwanted source/drain leakage conduction, or punchthrough current, and as such, are sometimes referred to as “punchthrough stoppers”.
Punchthrough current may also be seen as a parasitic current path existing between the drain and source, which is poorly controlled by the gate contact since the current path is located deeper in the bulk (substrate) farther from the gate. The actual amount of punchthrough current depends mainly on the potential distribution under the channel and on the S/D junction depths. As the effective channel length gets shorter, the S/D depletion regions also get closer. Punchthrough may then be established when the effective channel length is decreased to roughly the sum of the two junction depletion widths. One way to reduce the punchthrough current is to increase the overall bulk doping level. As a result, the drain and source depletion regions become smaller and may not establish a parasitic current path. Since a higher bulk doping increases the subthreshold swing, this method is not the most efficient way to reduce drain-source leakage.
Currently, super-sharp (SS) highly doped drain (HDD) profile junctions are commonly used to minimize channel resistance, extension region resistance, and source-drain resistance; (Rds) in a transistor. However, the SS HDD junction also increases the body-to-source/drain junction capacitance (Cqbw).
By contrast, graded HDD junction profiles have also been used to improve device performance; particularly with today's deep sub-micron technologies, graded HDD profiles improve circuit performance with lower Cjbw or tunneling current. Graded HDD junctions may also advantageously lower the body-to-source/drain junction capacitance Cjbw, lower the band-to-band tunneling current, and reduce channel dopant segregation into the HDD (S/D) region. Graded HDD junctions may also permit better trimming (compensation) of the HDD profile with super-sharp retrograde SSR channels, reduce
Brady III W. James
Garner Jacqueline J.
Lindsay Jr. Walter L.
Niebling John F.
Telecky , Jr. Frederick J.
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