Method to fabricate MIM capacitor using damascene process

Details Method to fabricate MIM capacitor using damascene process Method to fabricate MIM capacitor using damascene process

2001-11-13

2003-11-11

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S622000

Reexamination Certificate

active

06645810

ABSTRACT:

FIELD OF THE INVENTION
The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a novel metal-insulator-metal (MIM) capacitor and a method for forming such a capacitor.
BACKGROUND ART
As semiconductor geometries continue to become smaller and smaller, new difficulties arise in the fabrication of semiconductor devices. As one example, with progressively finer design rules, a problem has arisen due to capacitance between adjacent metal layers (i.e. interlayer capacitance). That is, as devices shrink in size, adjacent layers are spaced more closely together. Such a condition results in a deleterious increase in interlayer capacitance which adversely affects operation of finer design rule-based semiconductor devices. A similar problem exists due to the reduced distance between adjacent metal lines. Specifically, under some circumstances, unwanted effects such as cross-talk and various other RC (resistance/capacitance) delay effects between closely spaced metal lines negatively affect the operation of the semiconductor devices.
In one attempt to reduce such deleterious effects, newer semiconductor fabrication techniques are employing lower resistance metals (e.g. copper) to form many metal elements (e.g. lines, interconnects, and the like). Such newer semiconductor fabrication techniques include, for example, damascene/dual-damascene/multi-damascene processes which readily employ copper metal and which achieve highly desirable results. Unfortunately, copper, as an example, is not readily etched in the manner which conventionally-used aluminum, for example, is etched. As a result, certain structures, such as capacitors, which in the past have been readily formed, at least in-part, by the etching of aluminum, are not compatible with the newer semiconductor fabrication techniques such as, for example, copper damascene/dual-damascene/multi-damascene processes.
When forming huge copper plates, several problems such as dishing, cusping, and erosion occur. For example, using conventional chemical mechanical polishing (CMP), severe dishing may occur when the copper plates are larger than, for example, 8-10 micrometers. Therefore, large copper metal-insulator-metal (MIM) capacitors plates with a dimension larger than, for example, 10 micrometers by 10 micrometers are difficult to form with copper damascene/dual-damascene/multi-damascene processes.
As yet another concern, in order to achieve widespread acceptance, and to ensure affordability, any method of forming a capacitor, which overcomes the above-listed drawbacks, should be compatible with existing semiconductor fabrication processes.
Thus, a need exists for a capacitor and a method for forming the capacitor wherein the capacitor and the formation method are compatible with newer semiconductor fabrication techniques. A further need exists for a capacitor and a method for forming the capacitor wherein the capacitor and the formation method meet the above need and are compatible with existing semiconductor fabrication processes such that significant revamping of semiconductor capital equipment is not required.
SUMMARY OF INVENTION
The present invention provides a capacitor and a method for forming the capacitor wherein the capacitor and the formation method are compatible with newer semiconductor fabrication techniques. The present embodiment further provides a capacitor and a method for forming the capacitor wherein the capacitor and the formation method achieve the above-listed accomplishment and are compatible with existing semiconductor fabrication processes such that significant revamping of semiconductor capital equipment is not required. The present embodiment further provides a capacitor and a method for forming a capacitor with huge copper plates, for example, larger than 100 square micrometers.
In one method embodiment, the present invention recites forming a number of first openings in a first substrate. The present embodiment then recites forming a copper region within each first opening during a damascene process, wherein each copper region has a top surface. The present embodiment then disposes a dielectric layer proximate to the top surface of each of the first copper regions during the damascene process. After depositing a second substrate over the dielectric, a number of second openings in the second substrate are made. Next, a number of second copper regions are formed in the second openings, during the damascene process. The dielectric region is thus disposed between the first copper regions and the second copper regions. In so doing, the dielectric region forms a dielectric barrier between the first copper regions and the second copper regions such that a metal-insulator-metal (MIM) capacitor is formed during a damascene process.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.


REFERENCES:
patent: 6320244 (2001-11-01), Alers et al.
patent: 2002/0019123 (2002-02-01), Ma et al.
patent: 2002/0074584 (2002-06-01), Yang
patent: 2002/0102809 (2002-08-01), Barth et al.

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