Method to fabricate dish-free copper interconnects

Details Method to fabricate dish-free copper interconnects Method to fabricate dish-free copper interconnects

2002-02-08

2003-03-11

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S634000, C438S639000, C438S669000, C438S675000

Reexamination Certificate

active

06531386

ABSTRACT:

The present invention relates generally to fabrication of semiconductor devices, and more specifically to fabrication of metal interconnects used with semiconductor devices.
BACKGROUND OF THE INVENTION
Currently, the fabrication of each copper damascene level or layer requires three chemical mechanical planarization (CMP) steps with two different slurries. This copper fabrication process is complex and costly since two end-point detectors and two different slurries are needed. Further, dishing usually occurs in the copper interconnects during the second CMP step which removes the TaN etch stop layer. This is mainly due to the fact that TaN is harder and more inert compared to copper, thus dishing of the copper lines is inevitable.
U.S. Pat. No. 6,225,223 B1 to Liu et al. describes a selective copper interconnect process.
U.S. Pat. No. 6,184,138 B1 to Ho et al. describes a selective electroless copper plating process using a cap layer
18
.
U.S. Pat. No. 6,180,523 B1 to Lee et al. describes another selective copper interconnect formed over an underlying copper interconnect including a barrier layer
46
.
The Murakami et al. article entitled “Spin-on Cu Films for ULSI Metallization,” American Vacuum Society, 1
st
International Conference on micro-electronics and interfaces, Feb. 7 to 11, 2001, Santa Clara, California Convention Center, describes a spin-on copper (Cu) process.
The Rosenmayer et al. article entitled “An Oxide Cap Process for a PTFE-based IC Dielectric,” IEEE, 1998 describes a spin-on copper process to fill trenches and vias down to 0.3 &mgr;m.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved damascene process.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductive structure. The non-stick material layer having an upper surface. The non-stick material layer is patterned to form a patterned non-stick material layer having at least one trench therethrough exposing at least a portion of the at least one conductive structure. A metal interconnect is formed in contact with the exposed portion of the at least one conductive structure within the at least one trench wherein the non-stick properties of the patterned non-stick material layer prevent accumulation of the metal comprising the metal interconnect upon the patterned upper surface of the patterned non-stick material layer. The at least one metal interconnect having an upper surface. The patterned non-stick material layer is removed. A planarized dielectric layer is formed over the structure exposing the upper surface of the at least one metal interconnect.


REFERENCES:
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patent: 5928791 (1999-07-01), Rosenmayer
patent: 6180523 (2001-01-01), Lee et al.
patent: 6184138 (2001-02-01), Ho et al.
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Murakami et al., “Spin-on Cu Films for ULSI Metallization”, American Vacuum Society, 1st Int'l Conf. on microelectronics and interfaces, Feb. 1-11, 2001, Santa Clara, CA Convention Center.
Rosenmayer et al., “An Oxide Cap Process for a PTFE-Based IC Dielectric,” IEEE, 1998.

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