Method to fabricate deep sub-.mu.m CMOSFETS

Details Method to fabricate deep sub-.mu.m CMOSFETS Method to fabricate deep sub-.mu.m CMOSFETS

1998-02-06

2000-08-01

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438528, 438766, 438775, 257408, H01L 21336

Patent

active

060966149

ABSTRACT:
The method of the present invention is a method to fabricate a MOS device without boron penetration. After growing a gate oxide layer, a thin stacked-amorphous-silicon layer (SAS) is deposited over the oxide layer. Subsequently, a lightly nitrogen ion is implanted into the stacked-amorphous silicon layer. The stacked-amorphous silicon layer is patterned to define a gate structure. Then, a light doped ion implantation is performed to dope ions through the gate oxide layer into the substrate to form lightly doped source and drain regions. A dielectric layer is formed over the gate structure and the gate oxide layer, and the dielectric layer is etched to form sidewall spacers. Next, a second ion implantation is performed to dope ions into the substrate to form source and drain. Finally, a thermal annealing is performed on the stacked-amorphous silicon gate and the substrate. The nitrogen ions in the stacked-amorphous silicon gate are segregated into the gate oxide layer to act as a diffusive barrier, the stacked-amorphous silicon gate being convert into ploy silicon gate and thereby forming shallow source and drain junction in the substrate.

REFERENCES:
patent: 5628221 (1997-05-01), Chao et al.
patent: 5670397 (1997-09-01), Chang et al.
patent: 5710454 (1998-01-01), Wu
patent: 5767004 (1998-06-01), Balasubramanian et al.

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