Method to fabricate deep sub-&mgr;m CMOSFETs

Details Method to fabricate deep sub-&mgr;m CMOSFETs Method to fabricate deep sub-&mgr;m CMOSFETs

1999-07-01

2001-11-27

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06323094

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more specifically, to a method of fabricating a complementary metal oxide semiconductor field effect transistor (CMOSFET).
BACKGROUND OF THE INVENTION
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in the semiconductor technologies. For deep sub-micron high performance MOS ULSI application, as suggested in the reference “B. Davari, in IEDM Tech. Dig., p. 555, 1996.”, the dual poly gate CMOS technology (p+ poly gate for PMOSFET and n+ poly gate for NMOSFET) is necessary. However, as mentioned in“Y. Taur, et al., in IEDM Tech. Dig., p. 901, 1992.”, the effect of boron penetration through the thin gate oxide into silicon substrate will degrade the device performance. There are several methods to suppress the boron penetration effects, such as (1) N
2
O nitridation of thin gate oxide suggested in reference “E. Hasegawa, et al., in IEDM Tech. Dig., p. 327, 1995.”, (2) the heavy nitrogen implantation (dosage≧4E 15 cm−2) into poly-Si suggested in reference “S. Shimizu, et al., in IEDM Tech. Dig., p. 67, 1994.”, and (3) the stacked-Si layer as gate material suggested in “S. L. Wu, et al., in IEDM Tech. Dig., p. 329, 1993”, etc.
Although the heavy nitrogen implantation into poly-Si layer could effectively suppress the boron penetration effects, the sheet resistance of poly gate will be largely increased with increasing the nitrogen dosage for both n+ and p+ poly gates, especially for the nitrogen dosage larger than 4E15 cm
−2
. This is shown in the reference “S. Shimizu, et al., J. Appl. Phys., vol. 35, p. 802, 1996.”.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method to fabricate dual gate CMOS devices without boron penetration.
A second object of the present invention is to provide a method to fabricate dual gate CMOS devices for suppressing boron penetration without serious side effects. According to the objects of the invention, two approaches are disclosed to achieve them. The approaches are illustrated as follows.
In the first approach, a pad oxide layer is formed over a substrate, and then nitrogen ions are implanted into the pad oxide layer and substrate. After the pad oxide layer removed, a gate oxide layer is formed over the substrate by thermal oxidation treatment. In the period of oxidation, the doped nitrogen ions are incorporated into the gate oxide layer, thereby forming a nitrided gate oxide layer as a diffusion barrier to suppress boron penetration. After the formation of the nitrided gate oxide layer, at least one amorphous silicon layer is stacked on the nitrided gate oxide layer. Through patterning the stacked amorphous silicon (SAS) layer and nitrided gate oxide layer, a gate structure is formed, then forming source/drain with LDD regions in the substrate. Finally, by thermal treatment, the gate structure of SAS layer is converted into poly gate and the shallow junctions of the source/drain are formed.
In the other approach, a substrate with a gate oxide layer thereon, is placed in nitrogen plasma ambient, such as ICP and EVR system, thereby forming a nitrided gate oxide layer over the substrate. After the nitrided gate oxide formed, at least one SAS layer is stacked on the nitrided gate oxide layer. Thereafter, following the above procedure, source/drain/gate structures are formed in or on the substrate.
Therefore, summing up both the embodiments, the invention provides benefits of improving the gate reliability and without increasing the gate resistance dramatically, due to the formation of nitrided gate oxide and SAS gate electrode.


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