Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-08
2003-12-16
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S528000, C438S585000, C438S586000, C438S587000, C257S288000, C257S407000, C257S408000, C257S763000
Reexamination Certificate
active
06664153
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating a single gate having dual work-functions in the fabrication of integrated circuits.
(2) Description of the Prior Art
As technology progresses, enabling higher levels of integration within system integrated circuit chips, it will be essential to be able to fabricate semiconductor device gates that accommodate different work-functions within a single gate across a short device channel. Many mature methods can be used to fabricate such gates, either metal or silicon. However, these processes might be cumbersome or expensive.
U.S. Pat. No. 5,770,490 to Frenette et al discloses a dual work-function device wherein different gates have different work-functions depending on doping. U.S. Pat. No. 6,187,657 to Xiang et al shows a gate composed of dual gate materials. U.S. Pat. No. 5,620,906 to Yamaguchi et al teaches ion doping to form source/drain regions. U.S. Pat. No. 5,530,265 to Takemura and U.S. Pat. No. 6,235,574 to Tobben et al show doping processes.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the invention is to provide a process for forming a single gate having dual work-functions in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming a single gate having a dual work-function by means of plasma enhanced ion doping in the fabrication of integrated circuits.
Another object of the invention is to provide a process for forming a single gate having a dual work-function by means of selective plasma enhanced ion doping.
In accordance with the objects of the invention, a method for forming a single gate having a dual work-function is achieved. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.
REFERENCES:
patent: 4714519 (1987-12-01), Pfiester
patent: 4978626 (1990-12-01), Poon et al.
patent: 5108940 (1992-04-01), Williams
patent: 5530265 (1996-06-01), Takemura
patent: 5620906 (1997-04-01), Yamaguchi et al.
patent: 5759920 (1998-06-01), Burns, Jr. et al.
patent: 5770490 (1998-06-01), Frenette et al.
patent: 5804496 (1998-09-01), Duane
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6037247 (2000-03-01), Anand
patent: 6087225 (2000-07-01), Bronner et al.
patent: 6187657 (2001-02-01), Xiang et al.
patent: 6235574 (2001-05-01), Többen et al.
patent: 6300177 (2001-10-01), Sundaresan et al.
patent: 6365466 (2002-04-01), Krivokapic
Ang Chew Hoe
Cha Randall Cher Liang
Lim Eng Hua
Quek Elgin
Yen Daniel
Chartered Semiconductor Manufacturing Ltd.
Pham Long
Pike Rosemary L. S.
Rao Shrinivash
Saile George O.
LandOfFree
Method to fabricate a single gate with dual work-functions does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to fabricate a single gate with dual work-functions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to fabricate a single gate with dual work-functions will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3115109