Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-06
2002-02-19
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S232000
Reexamination Certificate
active
06348370
ABSTRACT:
CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
Patent No./Serial No.
Filing Date
TI Case No.
60/068,543
12/23/97
TI-23167
60/117,774
1/29/99
TI-28594
*
*
TI-
FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to a method for forming a general purpose self aligned source resistor in embedded flash memory applications
BACKGROUND OF THE INVENTION
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
The density of the microelectronic devices on the semiconductor substrate may be increased by decreasing spacing between each of the various semiconductor devices. The decrease in spacing allows a larger number of such microelectronic devices to be formed on the semiconductor substrate. As a result, the computing power and speed of the semiconductor component may be greatly improved.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells with each cell having a floating gate transistor. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each cell is a floating gate transistor having a source, drain, floating gate, and a control gate. The floating gate uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line.
Embedding FLASH memory circuits in CMOS logic circuits is finding increasing usage in building more complex integrated circuits such as digital signal processors for applications such as hard disk controllers. In addition to CMOS transistors and FLASH memory cells, it is necessary to have other components such as resistors as a part of the integrated circuits. These resistors are usually formed using polycyrstalline silicon which is commonly used to form the gate electrode. This polycrystalline (poly) resistor can be formed during the gate poly process where it is defined at the gate level and protected from silicidation by using an extra mask to prevent the sidewall dry etch from etching the nitride from the top of the resistor. Since the use of this extra mask is not desirable, attempts are being made to eliminate this mask. In applications where FLASH memory is used, this mask can be eliminated by using the poly-1 layer in the floating gate transistor to form the resistor. The sheet resistance of the poly-1 film is typically about 1500-2500 ohm/sq. For high frequency applications however, the capacitances associated with the poly-1 resistor and the floating/control gate structure make the resistance frequency dependent and therefore not suitable for use. The instant invention addresses this problem and describes a method for fabricating a general purpose self aligned source resistor in embedded FLASH applications.
SUMMARY OF THE INVENTION
The instant invention provides a method of forming a resistor in an integrated circuit containing FLASH memory cells. The method comprises: A method for forming a resistor in a semiconductor substrate comprising: providing a region of a first conductivity type in said semiconductor substrate; providing on said region of a first conductivity type, a plurality of substantially parallel wordlines that cross a plurality of substantially parallel isolation regions, said isolation regions containing an isolation material; implanting said region of a first conductivity type in said semiconductor substrate containing said plurality of substantially parallel wordlines and said plurality of substantially parallel isolation regions with a first species; etching said isolation material from all regions of said plurality of substantially parallel isolation regions not covered by said plurality of substantially parallel wordlines; and implanting said region of a first conductivity type in said semiconductor substrate containing said plurality of substantially parallel wordlines and said plurality of substantially parallel isolation regions with said first species to form a resistor.
REFERENCES:
patent: 6080625 (2000-06-01), Chittipeddi et al.
patent: 6090648 (2000-07-01), Reedy et al.
patent: 6218265 (2001-04-01), Colpani
patent: 0 545 363 (1993-06-01), None
Goodpaster Harold D.
Mehrad Freidoon
Seshadri Anand
Brady III W. James
Fourson George
McLarty Peter K.
Pham Thanh
Telecky , Jr. Frederick J.
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