Method to fabricate a robust and reliable memory device

Details Method to fabricate a robust and reliable memory device Method to fabricate a robust and reliable memory device

2000-04-04

2001-08-21

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000, C438S286000

Reexamination Certificate

active

06277691

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming non-volatile memories in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Non-volatile memory cells are an important device type in the art of integrated circuit manufacturing. Non-volatile memory cells, such as EEPROM, are used to hold vital data and programming information in computer systems for a variety of applications. Manufacture of non-volatile memory devices presents unique challenges.
Referring now to
FIG. 1
, a partially completed non-volatile memory cell is illustrated. Many such cells would be formed in a typical non-volatile memory integrated circuit device. A semiconductor substrate
10
is shown with shallow trench isolations (STI)
14
defining the device active area. The defining element of the non-volatile memory cell is the presence of a floating gate. A very thin dielectric layer, called a tunneling dielectric
18
overlies the semiconductor substrate
10
. The floating gate
22
is formed overlying the tunneling dielectric
18
. The floating gate
22
is comprised of a conductive material, such as doped polysilicon, that is not connected to any other circuit element. A second dielectric layer, called an interpoly dielectric
24
, overlies the floating gate
22
. Finally, the control gate
26
, comprising doped polysilicon, overlies the interpoly dielectric layer
24
.
At this point in the manufacturing process, the source and drain regions have not been formed. Once formed, the non-volatile memory cell is essentially a MOSFET with a variable threshold voltage. This threshold voltage varies according to the charge on the floating gate. Under certain conditions, electrons can be moved across the tunneling dielectric to either charge or discharge the floating gate
22
. The relative threshold voltage of the cell can then be detected by the sensing circuitry of the integrated circuit to decode the state (logic “0” or “1”) of the cell.
Referring now to
FIG. 2
, a masking layer
42
of photoresist has been applied overlying the entire surface of the integrated circuit wafer. This masking layer
42
has been patterned to expose a part of the cell. The focus of the exposed area in the semiconductor substrate
10
is the planned drain junction for the cell. The exposed area also overlaps onto the STI
14
and a part of the control gate
26
. The only openings formed in the masking layer
42
are for the planned drain junctions. As such, the majority of the integrated circuit surface area is covered by the masking layer
42
.
Referring now to
FIG. 3
, ions are implanted
46
into the surface of the semiconductor substrate
10
to form the heavily doped drain junctions
50
. The masking layer
42
shields the implantation
46
from all other parts of the circuit.
A potential problem
54
is depicted in the illustration. The ion implantation process involves focusing a beam of high energy ions
46
at the integrated circuit wafer. Ions that strike the photoresist layer
42
will cause a charge accumulation. This accumulation of charge is sometimes called the antenna effect. If a sufficient amount of charge accumulates in the photoresist layer
42
, a relatively large voltage potential may develop between the photoresist and the semiconductor substrate
10
. A flow of charge
54
into the semiconductor substrate
10
will then occur and may cause damage to the very thin tunneling dielectric
18
. Damage to the tunneling dielectric
18
will severely affect the yield, operation, and reliability of the memory cell.
Referring now to
FIG. 4
, a top view of the partially completed non-volatile memory cell is shown. The masking layer
42
covers most of the integrated circuit surface excepting the openings
72
made for the ion implantation. Because of the large surface area of the masking layer
42
of the prior art design, the masking layer
42
forms a large charge-capturing antenna.
Several prior art approaches disclose methods to deal with antenna effects in integrated circuit manufacturing processes. U.S. Pat. No. 5,350,710 to Hong et al discloses a method to form multilevel conductive interconnections using an anti-fuse device. Large metal contact pads, which may act as charge antennas during plasma processes, are connected to the integrated circuit through anti-fuse devices. The anti-fuse devices comprise a thin dielectric connected to a ground reference through a junction in the substrate. The anti-fuse device isolates the large pads from other circuitry. U.S. Pat. No. 5,393,701 to Ko et al teaches a process to eliminate plasma induced damage using temporary open circuits. Metal traces to large contact pads are purposely left open-circuited until all plasma processing is completed. The open circuits are then bridged. U.S. Pat. No. 5,783,366 to Chen et al discloses a method to improve scanning electron microscope (SEM) inspection capability for integrated circuit production wafers. The developed photoresist layer overlying the wafer is ion implanted to increase conductivity and to thereby improve SEM imaging. U.S. Pat. No. 5,869,877 to Patrick et al teaches an apparatus for measuring the voltage potential or current flow between the surface charge collector and the substrate due to plasma charging. The apparatus allows various surface topologies to be used in evaluation and optimization of plasma processes. U.S. Pat. No. 5,441,849 to Shiraishi et al discloses a process to reduce positional deviation of patterning processes. A bottom resist layer is made conductive by radiation exposure. This conductive resist layer reduces charge accumulation during the patterning process to thereby reduce positional deviation.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to form non-volatile memory cells in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to ion implant heavily doped junctions in the semiconductor substrate in the formation of non-volatile memory cells.
A still further object of the present invention is to prevent ion implantation induced damage to the tunneling dielectric by reducing the charge accumulating surface area of the implantation masking layer.
A yet still further object of the present invention is to improve the robustness and reliability of the non-volatile memory cell.
In accordance with the objects of this invention, a new method of forming non-volatile memory cells that prevents ion implantation induced damage in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A tunneling dielectric layer is formed overlying the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling dielectric layer. The first polysilicon layer and the tunneling dielectric layer are patterned to form floating gates. An interpoly dielectric layer is deposited overlying the floating gates and the semiconductor substrate. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are patterned to form control gates overlying the floating gates. A masking layer is deposited overlying the control gates and the semiconductor substrate. The masking layer is patterned to form implantation openings in the masking layer for planned heavily doped junctions and to form isolated rings of the masking layer surrounding the implantation openings. Ions are implanted through the implantation openings and into the semiconductor substrate to thereby complete the heavily doped junctions and the non-volatile memory cells in the manufacture of the integrated circuit device. The isolated rings of the masking layer do not induce charge flow into the tunneling dielectric layer.


REFERENCES:
patent: 4958321 (1990-09-01), Chang
patent: 5350710 (1994-09-01), Hong et al.
patent: 5393701 (1995-

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