Method to fabricate a new structure with multi-self-aligned...

Details Method to fabricate a new structure with multi-self-aligned... Method to fabricate a new structure with multi-self-aligned...

2000-02-18

2001-03-20

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S259000, C438S262000

Reexamination Certificate

active

06204126

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a split-gate flash memory cell having multi-self-aligned structure.
(2) Description of the Related Art
One of the important drivers for increased performance in computers is the higher levels of integration of circuits. This is accomplished by miniaturizing or shrinking device sizes on a given chip. Tolerances play an important role in being able to shrink dimensions on a chip. Self-alignment of various components in a device can help reduce those tolerances and improve packing density of chips. As is known in the art, a split-gate flash memory cell normally has a floating gate, a control gate, source and drain regions, and none of them are usually self-aligned with respect to each other. That is, floating gate is not aligned to the cell isolation regions, nor to the common source line, nor to the control gate, or word line. This is primarily because of the poly oxide process employed in forming the floating gate. Consequently, it is difficult to shrink such a device. It is disclosed later in the embodiments of the present invention a method of forming a multi-self-aligned structure where the memory cell can be substantially reduced in size with the attendant improved packing density and performance.
A method of forming a conventional split-gate flash memory cell is shown in
FIG. 1
a
where a layer of gate oxide (
30
) is thermally grown over substrate (
10
). Next, a first polysilicon layer (
40
) is formed followed by the deposition of nitride layer (
50
). A photoresist layer (
60
) is then spun over the substrate and then patterned with a floating gate pattern as shown in
FIG. 1
b
, which in turn, is etched into the nitride layer (
50
) as shown in
FIG. 1
c
. The photoresist layer, which is no longer needed, is removed. Next, the first polysilicon that is exposed in the pattern openings in the nitride layer is oxidized to form polyoxide (
45
) as shown in
FIG. 1
d
. Subsequently, the nitride layer is removed where now polyoxide (
45
) serves as a hard mask to remove all the first polysilicon portions except those that are covered by the polyoxide (
FIG. 1
e
). As is well known in the art, this is usually accomplished by main etch followed by over-etch. It is at this etching step that the corner edge (
47
) is usually rounded off, as seen in
FIG. 1
e
, which is not desirable for achieving fast program erase speed described below. It will be shown later in the embodiments of this invention that by employing a “smiling effect”, the sharpness of corner edge (
47
) can be improved such that charge transfer between substrate (
10
) and floating gate (
40
), and then the charge transfer between the floating gate and control gate, (
60
), is fast. The control gate is formed by depositing a second polysilicon layer over intergate layer (
50
), also known as interpoly, which separates the two polysilicon layers, namely, the floating polygate and the control polygate. The completed split-gate cell structure is shown in
FIG. 1
f.
Over the years, numerous improvements in the performance as well as in the size of memory devices have been made by varying the simple, basic one-transistor memory cell, which contains one transistor and one capacitor. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. In general, memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMS). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
FIG. 1
g
, which is an enlarged view of
FIG. 1
f
, is a conventional flash-EEPROM cell where two MOS transistors share a common source (
25
). A top view is shown in
FIG. 1
h
.
FIG. 1
g
is a cross-sectional view of the cell taken at
1
g
—
1
g
crossing active region (
15
) defined by passive filed oxide or isolation region (
13
). A top view of the shared common source line is referenced as (
70
) in
FIG. 1
h.
In the cross-sectional view
1
g
, the first doped region, (
20
), lies within the substrate. The second doped region, (
25
), also lies within substrate (
10
) and is spaced apart form the first doped region (
20
). Channel region (
23
) lies within substrate (
10
) and between first (
20
) and second (
25
) doped regions. Gate oxide layer (
30
) overlies substrate (
10
). Floating gate (
40
), to which there is no direct electrical connection, and which overlies substrate (
10
), is separated from substrate (
10
) by a thin layer of gate oxide (
30
) while control gate (
60
), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (
50
) therebetween.
To program the transistor shown in
FIG. 1
g
, charge is transferred from substrate (
10
) through gate oxide (
30
) and is stored on floating gate (
40
) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed “on” of “off.” “Reading” of the cell's state is accomplished by applying appropriate voltages to the cell source (
25
), Vs, drain (
20
), Vd, and to control gate (
60
), Vg, and then sensing the amount of charge on floating gate (
40
). To erase the contents of the cell, charges are removed from the floating gate by transferring them to the word line (control gate) through the gate oxide. The path of the charge transfer is shown by arrows (
41
) in
FIG. 1
g.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (FN) tunneling for erasing, and channel-hot electron (CHE) injection for programming, as is well known in the art. FN tunneling usually requires higher voltage than the CHE mechanism. It is common practice use FN tunneling for both write and erase for NAND type of cell architecture, while CHE programming and FN tunneling erasure is used for NOR circuits. The latter approach is shown in
FIG. 1
g
. Thus, in the programming mode, source (
25
) is coupled to the floating gate through a high voltage which in turn creates a high electric field between floating gate (
40
) and control gate (
60
), thereby causing injection of CHEs from substrate (
10
) to floating gate (
40
) in
FIG. 1
g
. In the erase mode, on the other hand, the control gate is impressed with a high voltage and electrons are injected from the floating gate to the control gate through the FN tunneling mechanism, usually aided by the poly tip of the floating gate.
In the conventional memory cell shown in
FIG. 1
g
, word lines (not shown) are connected to control gate (
60
) of the MOS transistor, while the length of the MOS transistor itself is defined by the source (
25
) drain (
20
) n+ regions shown in the same Figure. As is well known by those skilled in the art, the transistor channel is defined by masking the n+ regions. However, the channel length of the transistor varies depending upon the alignment of the floating gate (
40
) with the source and drain regions. This introduces significant variations in cell performance from die to die and from wafer to wafer. Furthermore, the uncertainty in the

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