Method to fabricate a MOSFET using selective epitaxial...

Details Method to fabricate a MOSFET using selective epitaxial... Method to fabricate a MOSFET using selective epitaxial...

1999-11-22

2001-09-04

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S299000, C438S489000, C438S607000

Reexamination Certificate

active

06284609

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the method of fabrication of integrated circuit devices, and more particularly, to a method of forming a sub-quarter-micron MOSFET structure with a raised source and drain in the fabrication of integrated circuits.
(2) Description of the Prior Art
In sub-quarter-micron MOSFET architecture, it is necessary to use ultra-shallow source and drain regions. Low energy ion implantation is typically used to form such regions.
For example,
FIG. 1
illustrates a semiconductor substrate
10
, preferably composed of monocrystalline silicon. A layer of silicon oxide
12
is formed on the surface of the substrate. A polysilicon layer is deposited and patterned to form gate electrode
16
. A typical LDD (lightly doped source and drain) structure is formed by an LDD mask implant followed by spacer oxide deposition and etching and then a source/drain mask implant. Lightly doped source and drain regions
20
are shown in FIG.
1
.
U.S. Pat. No. 5,200,352 to Pfiester teaches a method of forming a MOSFET device using raised epitaxial regions adjacent to lightly doped substrate source/drain regions allowing precise control of the source/drain region doping profiles. U.S. Pat. No. 5,447,874 to Grivna et al teaches a method of forming an MOSFET device using a dual metal gate formed in an oxide opening. Using a chemical mechanical polishing step to planarize the surface eliminates the problems encountered in etching different metals. U.S. Pat. No. 5,856,225 to Lee et al teaches of forming an MOSFET device where the source/drain regions are built prior to the implantation of the channel region under the gate. This allows more precise control of the source/drain positions, thereby controlling the electrical parameters of the MOSFET device.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a sub-quarter-micron MOSFET device having a raised source/drain structure.
Another object of the present invention is to provide a method of fabricating a sub-quarter-micron MOSFET device having a raised source/drain structure using selective epitaxial growth (SEG).
Yet another object of the present invention is to provide a method of fabricating a sub-quarter-micron MOSFET device having an LDD structure wherein the source/drain dopant concentrations are precisely controlled.
In accordance with the objects of this invention, a new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Shallow-trench isolation (STI) regions, for example, are formed in this substrate. An oxide layer is provided overlying both the substrate and the STI regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with in situ doping covering the two exposed substrate regions formed during the previous step. The doped SEG regions will form the source and drain contact regions of the MOSFET. The oxide layer region between the two doped SEG regions is then patterned and etched away exposing the substrate between the two doped SEG regions. This is followed by a gate oxide formation and either a polysilicon or metal gate deposition. Chemical mechanical polishing (CMP), for example, is then performed to planarize the surface to facilitate interconnection later in the process and forming the final gate structure. Thermal energy provided from processing steps or from a rapid thermal anneal (RTA) allows the doping atoms in the SEG regions to diffuse into the substrate forming the LDD regions. This method allows precise control of the doping profile in the LDD regions. An interlevel dielectric is then deposited over the entire surface. Contact holes are then etched in the interlevel dielectric and metalization patterned to allow interconnection to the completed MOSFET device.


REFERENCES:
patent: 4072545 (1978-02-01), De La Moneda
patent: 4419810 (1983-12-01), Riseman
patent: 4803173 (1989-02-01), Sill et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5447874 (1995-09-01), Grivna et al.
patent: 5856225 (1999-01-01), Lee et al.
patent: 6214680 (2001-04-01), Quek et al.
patent: 359082768-A (1984-05-01), None

Affiliated with

Also associated with

Rating

Method to fabricate a MOSFET using selective epitaxial... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to fabricate a MOSFET using selective epitaxial..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to fabricate a MOSFET using selective epitaxial... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2543556