Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-06
2001-05-15
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S321000, C257S319000, C257S322000, C365S185140, C438S261000, C438S558000
Reexamination Certificate
active
06232635
ABSTRACT:
TECHNICAL FIELD
This invention is related to a semiconductor flash cell. More particularly, the invention is directed to an improved method and article of manufacture of a flash cell with large enhancement of the capacitance coupling ratio between a control gate and a floating gate of the flash cell. The invention is further directed in particular to increasing overlap area between the floating gate and the control gate.
BACKGROUND OF THE INVENTION
Conventional semiconductor flash cells (see
FIGS. 1A and 1B
) have a very low coupling ratio between the control gate of polycrystalline silicon (poly 2) and the floating gate of polycrystalline silicon (poly 1). The coupling ratio is defined as C
2
/(C
1
+C
2
) where C
1
is the capacitance between the floating gate and substrate of the semiconductor device, and C
2
is the capacitance between the control gate and the floating gate. Performance parameters of the flash cell are unnecessarily degraded by having such a low coupling ratio. It is therefore important to develop a method and article of manufacture to increase the coupling ratio. Further, conventional flash cells usually have a tungsten silicide seam formed which creates substantial degradation of electrical performance.
SUMMARY OF THE INVENTION
According to one form of the invention, an article of manufacture is obtained by the method of (1) isolation formation in a conventional manner by local oxidation of silicon (LOCOS) or by shallow trench isolation (STI), (2) formation of an oxide on the LOCOS along with masking and etching, (3) tunnel oxide growth adjacent the oxide and LOCOS and deposition of polycrystalline silicon (poly 1), (4) masking and etching of the poly 1, (5) deposition of another polycrystalline silicon (poly 2) and a blanket etch back step which forms a poly 1 spacer, (6) growth of an oxide
itride/oxide layer (ONO), (7) deposition of a third polycrystalline silicon layer, (8) deposition of a silicide on the poly 2, (9) masking of the poly 2 and followed by conventional steps of processing a flash cell device structure.
These and other objects, features and advantages of the invention will be apparent from the following description of the preferred embodiments and examples, taken in conjunction with the accompanying drawings described hereinbelow.
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Avanzino Steven C.
Park Stephen Keetai
Shields Jeffrey A.
Wang Larry Yu
Advanced Micro Devices , Inc.
Foley & Lardner
Smith Matthew
Yevsikov V.
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