Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-01-05
2001-06-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S528000, C438S655000, C438S656000, C438S683000
Reexamination Certificate
active
06242333
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor devices and more particularly to a method for forming nucleation sites on silicon structures and an improved silicon structure.
BACKGROUND OF THE INVENTION
Titanium disilicide (TiSi
2
) is commonly used as a salicide (Self-Aligned siLICIDE) material in state-of-the-art CMOS device processes. The salicide process is a key step in reducing the sheet resistance of the small dimension gate and source and drain (S/D) regions of a device. Keeping the sheet resistance of these regions low is critical to the operation of high performance CMOS devices and integrated circuits.
At the heart of the standard salicide process using TiSi
2
is the formation of the C49 phase TiSi
2
(i.e., high resistance state) from deposited titanium (Ti) and the subsequent transformation of this silicide to C54 phase TiSi
2
(i.e., low resistance state). Traditionally, the formation is achieved with a second anneal following selective removal of unreacted Ti and titanium nitride (TiN).
In more detailed terms, a layer of Ti is deposited over the semiconductor structure. The layer is then subjected to a process to form a layer of C49 phase TiSi
2
, for example, an annealing process. When an annealing process is used, it is typically performed in a nitrogen ambient, so that the remaining non-silicided material is either unchanged or forms a metal nitride. A wet etch may then be used to selectively remove the non-silicided metal. In the case of Ti, a solution of H
2
O
2
and H
2
O may be used to wet etch the TiN which is formed during the annealing process, thus, leaving a layer of C49 phase TiSi
2
. To initiate the C49 to C54 transformation, a second anneal is performed. To successfully transform, however, a sufficient number of C54 nucleation sites must be present in the TiSi
2
. If not enough sites are present, then there will be incomplete transformation of the silicide for the given anneal conditions.
This C49 to C54 nucleation phenomenon manifests itself in the “poly linewidth effect” where it is observed that it becomes increasingly more difficult to form low sheet resistance (C54 phase) TiSi
2
on polysilicon lines having a width of less than about 1 &mgr;m. As the dimensions of the gate shrink below this width, fewer and fewer C54 nucleation sites exist that can aid in the C49 to C54 transformation (e.g., when the dimension of the structure to be silicided is of the same order or smaller than the average distance between C54 nuclei).
This problem has been partially solved by introducing more C54 nucleation sites into the narrow polysilicon or silicon regions using ion implantation to “roughen” by damaging the surface of the material to be silicided. This approach, referred to as PAI (Pre-Amorphization Implantation), has been successfully demonstrated as being usable to obtain low sheet resistance TiSi
2
on narrow (<0.25 &mgr;m) polysilicon lines. However, this approach suffers from the problem that the roughening/damaging created extends beyond the surface of the silicon and into the S/D regions of the device leads to increased diode junction leakage which degrades overall device performance.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a method for forming nucleation sites on silicon structures without introducing damage or metallic impurities into the underlying or adjacent silicon S/D regions. Also, a need has arise for an improved silicon structure. According to the teachings of the present invention, such a method and improved silicon structure are provided that address the disadvantages and problems associated with previous methods for forming nucleation sites on silicon structures and previous silicon structures.
A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the steps of: forming at least one nucleation region adjacent the narrow silicon structure; masking the at least one narrow silicon structure with a mask; treating the at least one nucleation region to enhance an ability of the nucleation region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure.
In another embodiment, a method for forming a low resistance silicide layer on an integrated circuit comprises: forming a first oxide layer over a semiconductor body; depositing a polysilicon layer over the first oxide layer; selectively etching the polysilicon layer and the first oxide layer to form at least one silicon structure and at least one nucleation region attached to the at least one silicon structure, the at least one nucleation region having a width which is greater than a distance separating C54 nuclei; siliciding the at least one silicon structure and the at least one nucleation region to form a layer of C49 phase silicide; and annealing the C49 phase silicide to form C54 phase silicide.
In still another embodiment, a semiconductor device capable of undergoing a phase transformation comprises: at least one narrow silicon structure; and at least one nucleation region attached to the at least one narrow silicon structure, the at least one nucleation region having a width which is greater than a width of the at least one narrow silicon structure and the at least one nucleation region capable of generating a high density of C54 nucleation sites such that the high density of C54 nucleation sites causes a phase transformation to propagate along the at least one silicon structure.
A technical advantage of the present invention is that a method for forming nucleation sites on silicon structures is provided. Another technical advantage is that a semiconductor device capable of undergoing a phase transformation is provided. Another technical advantage is that at least one nucleation region is used to induce the formation of localized nucleation sites. Another technical advantage is that a single nucleation region may be used to form nucleation sites on a plurality of narrow silicon structures. Another technical advantage is that more than one nucleation region may be used to form nucleation sites on an elongate silicon structure. Another technical advantage is that low resistance C54 state TiSi
2
may be formed on narrow silicon structures. Another technical advantage is that pre-amorphization implantation may be used to induce the formation of nucleation sites without damaging the active area of the device. Another technical advantage is that the introduction of refractory metals, for example, Mo, Ta and W, may be used to induce the formation of nucleation sites without damaging the active area of the device. Another technical advantage is that a method of transforming C49 phase silicide into C54 phase silicide is provided without the introduction of metallic impurities or other defects and damage into the S/D regions that may lead to higher diode junction leakage in the device being formed.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 4735680 (1988-04-01), Yen
patent: 5196360 (1993-03-01), Doan et al.
patent: 5510295 (1996-04-01), Cabral, Jr. et al.
patent: 5593924 (1997-01-01), Apte et al.
patent: 5856698 (1999-01-01), Hu et al.
patent: 6004871 (1999-12-01), Kittl et al.
Kittl et al.; “Novel one-step RTP Ti Salicide Process with Low Sheet Resistance 0.06 micron gates and High Drive Current”, IEEE, pp. 5.4.1-5.4.4.
Kittl Jorge Adrian
McNeil Vincent Maurice
Brady III W. James
McLarty Peter K.
Niebling John F.
Pompey Ron
Telecky , Jr. Frederick J.
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