Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-30
2001-09-04
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S632000, C438S957000
Reexamination Certificate
active
06284590
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating a metal-insulator-metal capacitor, and more particularly, to a method of forming a metal-insulator-metal capacitor without metal corner erosion in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors matching for metal-insulator-metal (MIM) capacitors in RF mixed signal applications is increasingly critical owing to stringent requirements. Nevertheless, process-instigated issues present major obstacles to efficient capacitor matching. One major process-instigated issue is varying capacitor characteristics owing to different extents of top metal erosion during bottom metal electrode patterning. Because of relatively poor etch selectivity between photoresist and metal, and because of thinner resist thickness lining the top metal electrode, especially along the sidewalls and top edges, the corners of the top metal electrode will be aggressively etched. This results in jagged edges at the top metal or corner rounding of the top metal electrode. The degree of etching or rounding differs from capacitor to capacitor and is uncontrollable. This makes capacitor matching for MIM in mixed signal applications difficult. It is desired to find a method to eliminate top metal corner shaping during bottom metal patterning of MIM capacitors.
U.S. Pat. No. 6,083,785 to Segawa et al shows a MIM capacitor process in which sidewall spacers are formed on a top polysilicon electrode over a resistor after patterning of the polysilicon structures. U.S. Pat. No. 5,998,264 to Wu, U.S. Pat. No. 6,037,206 to Huang et al, and U.S. Pat. No. 5,812,364 to Oku et al show various MIM capacitor processes.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor.
Another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated.
Yet another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated by the presence of sidewall spacers on the top metal electrode.
In accordance with the objects of this invention, a method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is achieved. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode and anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer. The capacitor dielectric layer and the first metal layer are patterned wherein the patterned first metal layer forms a bottom metal electrode and wherein the spacers protect the top metal layer from etching during the capacitor dielectric and bottom metal electrode patterning. The photoresist mask is removed, completing fabrication of a metal-insulator-metal capacitor.
REFERENCES:
patent: 3894872 (1975-07-01), Mitchell, Jr. et al.
patent: 5622893 (1997-04-01), Summerfelt et al.
patent: 5812364 (1998-09-01), Oku et al.
patent: 5918135 (1999-06-01), Lee et al.
patent: 5998264 (1999-12-01), Wu
patent: 6037206 (2000-03-01), Huang et al.
patent: 6083785 (2000-07-01), Segawa et al.
patent: 6200629 (2001-03-01), Sun
patent: 2000022083 (2000-01-01), None
Cha Randall Cher Liang
Chu Shao-Fu Sanford
Lee Tae Jong
Ng Cheng Yeow
Tee Chua Chee
Chartered Semiconductor Manufacturing Ltd.
Chaudhari Chandra
Pike Rosemary L. S.
Saile George O.
LandOfFree
Method to eliminate top metal corner shaping during bottom... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to eliminate top metal corner shaping during bottom..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to eliminate top metal corner shaping during bottom... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2528131