Method to eliminate shorts between adjacent contacts due to...

Details Method to eliminate shorts between adjacent contacts due to... Method to eliminate shorts between adjacent contacts due to...

1999-05-25

2002-04-02

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000, C257S277000, C257S403000

Reexamination Certificate

active

06365464

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more particularly, to a method to eliminate shorts between adjacent contacts due to interlevel dielectric voids in the manufacture of integrated circuits.
(2) Description of the Prior Art
Feature size reduction is essential for realizing increased device content and higher switching speeds on integrated circuits. This size reduction trend is especially true for dynamic random access memory (DRAM) technology where device sizes of 0.25 microns are now in fabrication. At physical dimensions this small, it is often difficult to deposit dielectric material over very closely spaced features without creating gaps or voids in the dielectric material.
In
FIG. 1
, a cross-section of a partially-completed DRAM integrated circuit is shown. Two wordline transistors
50
are shown with gate dielectrics of silicon oxide
14
, polysilicon gate nodes
18
, and silicon nitride sidewalls
26
and caps
22
. Heavily doped and lightly doped sources and drains
30
and
34
, respectively, have been implanted into a semiconductor substrate
10
. A layer of dielectric
38
comprised of silicon oxide overlays the wordline transistors
50
and the surface of the substrate
10
.
A problem typical to the art is shown in FIG.
1
. The wordline transistors
50
have a spacing S
1
of about 0.25 microns. At this close spacing, air gaps, voids, or keyholes
42
will form in the dielectric oxide layer
38
in the area between the two wordlines. These air gaps can be either helpful or harmful to the integrated circuit depending on subsequent processing. Air gaps in the dielectric can be helpful because the dielectric constant of air is much less than that of silicon oxide. The capacitive coupling between the two transistors can be reduced by the air gap. This improves circuit performance. These voids can cause real problems, however, in situations where the compromised integrity of the dielectric can allow a shorting condition to occur.
FIG.
2
and
FIG. 3
show what happens if a contact opening is created in the area where the dielectric void has occurred. Referring to
FIG. 2
, a contact opening has been etched through the dielectric layer
38
to the surface of the substrate
10
to allow contact between the bitline of the DRAM and the circuitry above the dielectric layer. The contact hole vertically intersects the void
42
. Void
42
is shown in the background of the cross section depicted in FIG.
2
. Effectively, the void constitutes a shaft extending from the contact hole out into the dielectric layer. A metal layer
54
is shown deposited overlying the dielectric layer and filling the contact hole. Unfortunately, the metal layer also fills the void
42
. Metal material in the void represents a definite risk for shorting out the circuit.
Referring now to
FIG. 3
, the problem is shown more fully depicted.
FIG. 3
represents a top view of the partially-completed structure shown in FIG.
2
. In
FIG. 3
, two adjacent contact holes are shown which lie between the two closely spaced MOS gate wordlines
50
. Both of the contacts are filled with metal layer
54
. To work properly, each contact hole must be physically and electrically isolated from the other by the dielectric layer
38
. Unfortunately, the void
42
in the dielectric layer
38
runs from one contact opening to the other and is causing each of the contact holes to be shorted together by the metal layer contained in the void.
Several prior art approaches attempt to address the problems of air voids in the dielectric layer. U.S. Pat. No. 5,665,657 to Lee teaches a method to remove voids in spin-on glass layers by using an etch and fill method. U.S. Pat. No. 5,728,631 to Wang discloses a method to form low capacitance dielectric voids between adjacent metal lines by an electrocyclotron resonance etching deposition technique. U.S. Pat. No. 5,783,481 to Brennan et al teaches a method to form air gaps in the interlevel dielectric by using polyimide film.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating contact openings in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate contact openings that prevents conductive shorts caused by air voids in the dielectric layer between narrowly-spaced adjacent conductive lines.
Another object of the present invention is to provide a method to prevent conductive shorts caused by air voids in the dielectric layer between narrowly-spaced adjacent conductive lines by lining contact openings with an insulating dielectric layer to fill exposed voids.
In accordance with the objects of this invention, a new method for fabricating contact openings in an integrated circuit is achieved. This method prevents conductive shorts caused by air voids in the dielectric layer between narrowly spaced adjacent conductive lines. An insulating dielectric layer is used to line contact openings and to fill any exposed voids. A semiconductor substrate is provided having narrowly spaced first conductive lines. The conductive lines may be MOS transistor gates, metal traces, or polysilicon traces. A dielectric layer is formed overlying the first conductive lines and the substrate. Contact openings are etched through the dielectric layer as defined by lithography. An insulating oxide layer is deposited overlying the dielectric layer and lining the contact openings. The insulating lining fills any dielectric air voids exposed by the contact opening etch. A conductive layer is deposited filling the contact openings and overlying the dielectric layer. The conductive layer is etched to define connectivity as defined by lithography. A passivation layer is deposited overlying the conductive layer and the dielectric layer to complete the integrated circuit.


REFERENCES:
patent: 5665657 (1997-09-01), Lee
patent: 5728596 (1998-03-01), Prall
patent: 5728631 (1998-03-01), Wang
patent: 5783481 (1998-07-01), Brennan et al.
patent: 5905293 (1999-05-01), Jeng et al.
patent: 5914518 (1999-06-01), Nguyen et al.

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