Method to eliminate dishing of copper interconnects

Details Method to eliminate dishing of copper interconnects Method to eliminate dishing of copper interconnects

1999-08-16

2001-05-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000

Reexamination Certificate

active

06225223

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the formation of metal interconnects in microminiaturized integrated circuits and more specifically to methods for the formation of copper interconnects in microminiaturized integrated circuits in semiconductor devices.
BACKGROUND OF THE INVENTION
The copper (Cu) damascene method has become mainstream in the manufacture of copper interconnects in microminiaturized integrated circuits (IC). Currently, chemical mechanical polishing (CMP) of the copper layers causes dishing of the copper interconnects. This dishing causes reduced yields, reliability and unacceptable performance. The deleterious effects of dished copper interconnects accumulate interconnect level by interconnect level.
U.S. Pat No. 5,723,387 to Chen discloses a self-contained unit for forming copper metallurgy interconnection structures on semiconductor (SC) substrates that provides a way of reducing the number of times the wafer is transferred between the less environmentally clean wet process steps and very clean dry process steps. The copper may be deposited over and into a barrier layer lined substrate surface and groove by electroless and electroplating techniques. The copper layer is then polished to expose the barrier layer which is then etched away. The copper is then polished to planarize it with the substrate surface and a second barrier layer is selectively deposited on the copper by electroless plating techniques. After cleaning and drying, a second dielectric layer is applied and the steps are repeated to form additional metallurgy layers.
U.S. Pat. No. 5,308,796 to Feldman et al. discloses a selective copper plating process where palladium silicide is used as a catalytic surface. Copper plating is introduced only where the silicide is present.
U.S. Pat. No. 5,298,058 to Matsui et al. discloses an electroless copper plating bath comprising a water soluble copper salt, a complexing agent, and a reducing agent consisting of phosphorous acid or a phosphite. The bath is less expensive than conventional plating baths using hypophosphorous acid.
U.S. Pat. No. 5,603,768 to Yoon et al. discloses an apparatus using flow-inducing panels for electroless copper plating of complex plastic microwave assemblies.
U.S. Pat. No. 5,695,810 to Dubin et al. discloses a CoWP barrier layer and electroless copper interconnect processes.
U.S. Pat. No. 5,674,787 to Zhao et al. discloses an electroless copper deposition technique to form interconnects that does not require CMP to planarize the plug surface after selective formation of the plug in the via opening.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved method of forming copper interconnects.
Another object of the present invention is to provide an improved method of forming planarized copper interconnects facilitating well controlled photo, etching, thin film and chemical mechanical polishing (CMP) processes.
A further object of the present invention is to provide an improved method of forming copper interconnects by of a second electroless plated copper layer.
Yet another object of the present invention is to provide an improved method of forming copper interconnects by CMP of a second chemical vapor deposited copper layer.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a dielectric layer is formed on a semiconductor structure. A trench is formed through the dielectric layer. A barrier layer is then deposited on the dielectric layer and in the trench. A first copper (Cu) layer is formed by depositing Cu on the barrier layer filling the trench and blanket filling the dielectric layer. The first Cu layer and the barrier layer on the upper surface of the semiconductor structure are planarized by chemical mechanical polishing (CMP), exposing the upper surface of the dielectric layer and leaving a dished Cu filled trench. Copper is then selectively deposited on the dished Cu filled trench either by electroless plating or chemical vapor deposition forming a second Cu layer extending above the upper surface of the dielectric layer. The second Cu layer is then planarized level with the upper surface of the dielectric layer forming a Cu interconnect.


REFERENCES:
patent: 5298058 (1994-03-01), Matsui et al.
patent: 5308796 (1994-05-01), Feldman et al.
patent: 5603768 (1997-02-01), Yoon et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5723387 (1998-03-01), Chen
patent: 5935762 (1999-08-01), Dai et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5993686 (1999-11-01), Streinz et al.
patent: 6100195 (2000-08-01), Chan et al.

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