Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-05
2003-04-22
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06553559
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit (IC) manufacture, and more particularly to the correction of line-width deviations in optical lithography systems used to print a pattern on a photoresist layer on a semiconductor wafer.
2. Background Description
There is a continuing effort to reduce the dimensions of integrated circuit (IC) devices, and this has required greater precision in the tools used to manufacture IC devices. IC devices are designed using computer-aided design (CAD) layout tools which allow chip manufacturers to plan the layout of the circuits on a semiconductor wafer. The finished designs must be transferred to the wafer in a manner that allows device features to be produced by various processes of etching, depositing, implanting, and the like. This is done by applying a photoresist layer to the surface of the wafer and then exposing the photoresist with radiation through a mask having a pattern of transparent and opaque areas according to the feature to be formed. The photoresist is developed to provide openings in the photoresist layer through which the surface of the wafer is exposed for the process desired. This process of transferring the pattern to the wafer is generally referred to as photolithography.
In order to optimize the photolithography process, a process window is computed to print a feature or features of interest under various conditions. The process window is computed by measuring the size of the feature(s) while varying the exposure dose and focus of the exposure system. This process window has proven quite useful in showing how tolerant a feature is to varying amounts of process errors. The difficulty with this method, however, is that the resulting process window is not a single number but instead a function typically given by depth of focus (DOF) as a function of exposure latitude (EL).
Various methods are used to reduce this function to a single figure of merit, but to this point no method has delivered a figure of merit that accurately represents the expected performance of a real process. However, approximations to this can be made by computing a single value from the DOF vs. EL function. These values can include the max DOF, max EL or total window, which is the area under the DOF vs. EL function.
As feature sizes shrink more rapidly than exposure wavelength (actually the k
1
factor is shrinking, where k
1
=min_half_pitch/(lambda/NA), where lambda is the wavelength and NA is the stepper's numerical aperture) and CD tolerances become more and more stringent, process windows are becoming extremely small. This drives the need for improved tooling and process control, along with more accurate process optimization methods. The rapid reduction in process window can be mitigated through the use of various resolution enhancement techniques. However, these techniques come at a cost: the need for optical proximity correction (OPC).
At low k
1
imaging, significant modifications to mask designs are required to print features in the desired fashion on the wafer. Due to the extreme sensitivity of many of these features to errors on the mask, in the stepper lens or in the lithography process (focus and dose), it is critical that these mask design modifications be done properly. This entails two major components. The first is the generation of accurate rules for the modifications, and the second is the correct interpretation of these rules into design modifications. The second component is addressed by the optical proximity correction (OPC) software. This invention addresses the first component.
The current industry standard method for generating OPC and assist feature rules is to design test structures and measure the size of the structures after they have been printed on the wafer (this printing can be done physically or through simulation). Typically, interpolation is used to determine both the optimum mask dimension for any pitch that is contained in the set of test structures and also to determine biases for pitches that are not contained in this set. In this way, corrections can be determined from a set of test structures that spans the range of sizes and pitches in the design, but only samples this range. This is typically done at a single dose and focus value, and using a single point in the field for any given test structure. Therefore, this method may only account for a small subset of the systemic errors in the mask making or lithography process (e.g., nested-isolated bias) and can not account for any random errors in these processes. Furthermore, these random errors may confound the correction rules.
SUMMARY OF THE INVENTION
According to the invention, there is provided a method of generating OPC and assist feature rules which provide improved wafer performance under typical manufacturing variations. This method relies on finding common process windows or weighted process windows of test structures, so that the impact of focus and dose variations can be determined. Whereas, a common process window is computed by finding the overlap of two or more process windows, it suffers from the same drawbacks as an individual process window (namely, it is a function, not a single value, and it does not utilize real process information). A weighted process window (WPW), and, likewise, a weighted common process window, does not suffer from these limitations.
The process window (PW) or WPW for a pattern is computed by first finding the exposure-defocus (ED) tree for that pattern. The ED tree is a series of curves that represent the focus and dose conditions for a given pattern to print at its critical dimension (CD) tolerance limits. The area contained inside the curves represents process conditions (focus and dose) that yield patterns that are within specifications on the wafer, while the area outside of the curves represent process conditions that yield patterns that are either too large or too small on the wafer. The area can be further reduced by adding cut-offs where the pattern either falls over or does not print at all and a side lobe cutoff that represents conditions where undesirable side lobes print. At this point, a process window is computed by fitting rectangles inside the ED tree curves and then plotting the height of the rectangle versus its width. This gives a DOF vs. EL curve.
Alternatively, the WPW is computed by incorporating information on the expected focus and dose variations. These variations are represented statistically and could be taken independently or as a coupled distribution. These distributions must be known prior to computing the WPW and can be determined using experimental test structures. Standard focus and dose variation distributions are often approximated by Gaussian curves that are specified by their center location (focus and dose) and a measurement of their extent, sigma. These types of Gaussian distributions, or other types that better match the data can be centered inside the given ED tree and used as weighting functions. The WPW is then computed by finding the weighted area inside the ED tree, as given by
WPW(E
0
,F
0
)=&Sgr;&Sgr;PW(F,E) DE(E;E
0
) DF(F;F
0
) dE dF,
where PW(F,E)=1 inside the ED tree curves, 0 outside the ED tree curves, and DE(E;E
0
) and DF(F;F
0
) are the distributions for dose (E) and focus (F) centered at E
0
and F
0
. E is typically given as log(Dose). The summations are theoretically over all focus and dose conditions, but in practice are limited by the finite extent of the non-zero region of PW(F,E).
Both the PW and WPW computations can be further expanded to account for other errors, such as mask CD errors or lens aberrations. By considering these variables in a manner similar to focus and dose, multidimensional functions can be computed that map out the conditions where the wafer image is within its tolerances. From these functions, multidimensional PW's or WPW's can be computed that quantify the pattern's tolerance to the given error components.
Finally, once the PW
Liebmann Lars W.
Mansfield Scott
Wong Alfred K.
C. Li Todd M.
Lin Sun James
Siek Vuthe
Whitham Curtis & Christofferson, P.C.
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