Method to detect systematic defects in VLSI manufacturing

Details Method to detect systematic defects in VLSI manufacturing Method to detect systematic defects in VLSI manufacturing

2005-04-12

2005-04-12

Thompson, Craig A. (Department: 2813)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C438S010000, C438S017000

Reexamination Certificate

active

06880136

ABSTRACT:
Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.

REFERENCES:
patent: 4503536 (1985-03-01), Panzer
patent: 4835458 (1989-05-01), Kim
patent: 5239262 (1993-08-01), Grutzner et al.
patent: 5297151 (1994-03-01), Gruetzner et al.
patent: 5414716 (1995-05-01), Bershteyn
patent: 5485471 (1996-01-01), Bershteyn
patent: 5497381 (1996-03-01), O'Donoghue
patent: 5515384 (1996-05-01), Horton, III
patent: 5652754 (1997-07-01), Pizzica
patent: 5727000 (1998-03-01), Pizzica
patent: 6018813 (2000-01-01), Chakradhar et al.
Groce, Jason, International Sematech. Technology Transfer # 99053735A-TR “Advanced Process Control Framework Initiative (APCFI) Project: Overview” Jun. 30, 1999 <<http://www/sematech.org/docubase/document/3735atr.pdf>>.*
Groce, Jason, International Sematech. Technology Transfer # 99053736A-TR “Advanced Process Control Framework Initiative (APCFI) Project: Detailed System Description” Jun. 30, 1999 <<http:www.sematech.org/docubase/document/3736atr.pdf>>.*
M.S.Hall, R.B.Hitchcock, Sr. and J.L. Rivero; IBM Technical Disclosure Bulletin, vol. 27, No. 10A, Mar. 1985.

Affiliated with

Also associated with

Rating

Method to detect systematic defects in VLSI manufacturing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to detect systematic defects in VLSI manufacturing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to detect systematic defects in VLSI manufacturing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3414969