Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-30
2003-01-07
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S321000, C438S258000
Reexamination Certificate
active
06504207
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to an EEPROM (Electronically Erasable Programmable Read Only Memory) structure, and in particular, an EEPROM memory structure integrated with high performance logic or non-volatile random access memory (NVRAM).
DESCRIPTION OF THE RELATED ART
A conventional EEPROM device generally includes a program gate, a floating gate, and a single select device wordline. During manufacturing, the program gate and floating gate must be aligned to a thin oxide tunnel region. Also, multiple masking steps are necessary to form the floating gate, program gate, and source/drain implantations. Further, the oxide tunnel region, located between the floating gate and an n
−
-type region of a silicon substrate must be sufficiently thin (e.g. 8 to 11 nm) to permit electrons to tunnel between the floating gate and the silicon substrate.
An example of a conventional EEPROM device fabrication can be found in U.S. Pat. No. 5,081,054 and its associated re-issue U.S. Pat. No. Re. 35,094.
Referring to
FIG. 1
, erasing a conventional EEPROM device
10
occurs by applying a sufficient voltage to program gate
11
to allow electrons to tunnel through a tunnel oxide region
12
located over the n
−
-type region
13
. Typically, a voltage of 15 volts is necessary to allow electron tunneling. Further, the tunnel oxide
12
must be thin enough to allow electron tunneling to occur at the applied bias conditions.
Electrons that tunnel from the data node
13
to the floating gate
14
as depicted by arrow
18
remain there and give the floating gate
14
a negative charge. Standard bias conditions to erase a conventional EEPROM device generally utilize a setting source
15
, drain bitline
16
and wordline
17
connect to ground.
A conventional EEPROM has only a single wordline since isolation of the data node (tile diffusion between the wordline gate and the floating gate
14
(i.e., data node), and its extension under the floating gate
14
) during a programming operation requires only one wordline. The erase operation is done in a page mode per wordline) and does not require isolation.
The conventional EEPROM requires one erase operations before it is programmed selectively as either “1” or “0”. More specifically, referring to
FIG. 2
, a conventional EEPROM device
20
is programmed to a “1” by applying a 5 volt signal to bitline
26
. The silicon surface potential of the n
−
-type region
23
is therefore fixed at 5 volts and is sufficient to produce an electric field across the tunnel oxide
22
to allow electron tunneling between the floating gate
24
and the n
−
-type region
23
of the substrate. Following this operation, the floating gate
24
has a positive potential as a result of electrons tunneling between the floating gate and the n
−
-type region
23
as depicted by arrow
28
.
Referring to
FIG. 3
, the EEPROM
30
is programmed to “0” by setting the voltage potential at bitline
36
and consequently the silicon surface potential in the n
−
-type region
33
to 0 volts. In addition, the source
35
is set to ground, the program gate
31
is set to −10 volts and wordline
37
is set to +5 volts. The electric field across the tunnel oxide
32
is insufficient to initiate electron tunneling between the floating gate
34
and the n
−
-type region
32
. As a result, the floating gate
32
charge remains at its erased value.
One disadvantage with conventional EEPROM manufacturing is the use of multiple masking steps to form a floating gate, a program gate, and source/drain implantations. Further, in conventional EEPROM manufacturing, the program gate and floating gate have to be aligned to a thin oxide tunnel region of the substrate. Such additional steps and alignment add costs and complexity to the manufacturing of conventional EEPROM devices.
An additional disadvantage with conventional EEPROM devices is the requirement of relatively high voltages, e.g. around 15 volts, to initially erase the conventional EEPROM memory device.
A third disadvantage of conventional EEPROM devices is the requirement of manufacturing a thin tunnel oxide between the floating gate and the n
−
-type region of the silicon substrate to allow electron tunneling when a sufficient voltage is applied to the program gate.
A fourth disadvantage of conventional EEPROM devices is the possibility of damage to the floating gate oxide through multiple program/erase cycles. As a result, the operation of the memory cell could be affected during read operations.
A fifth disadvantage of the conventional EEPROM is that the fabrication process interferes with the limited thermal budgets of high performance CMOS logic processes in embedded EEPROM applications.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional EEPROM device, the present invention has been devised , and it is an object of the present invention to provide a structure and method for an EEPROM device in which electron tunneling occurs between a floating gate and a program gate during programming. The electric field between the floating gate and the program gate can be enhanced by the use of silicon rich oxide on the facing surfaces of the floating gate and the program gate. As a result of the electron tunneling between the floating gate and the program gate, the voltage necessary to erase the EEPROM device is less than the voltage required to erase conventional EEPROM devices.
An additional object of the present invention is to provide an EEPROM device having a floating gate and program gate self-aligned with one another whereby not requiring additional masking and etching steps to achieve proper alignment.
Another object is to provide an EEPROM device integrateable with high performance logic (e.g. complementary metal oxide semiconductor (CMOS)) or non-volatile random access memory (NVRAM) and a bidirectional polysilicon to polysilicon EEPROM device.
According to one aspect of the invention, the memory device is formed on a silicon substrate. The memory device includes a floating gate, a program gate, and at least one select device. During programming of the memory device, electrons tunnel between the program gate and the floating gate.
According to another aspect of the invention, a memory device is formed on a silicon substrate. The memory device includes a floating gate, a program gate, a first select device and a second select device. In one form, thereof, the floating gate is formed of an amorphous polysilicon between two oxide layers.
According to yet another aspect of the invention, a memory device is formed on a substrate having layers of a base silicon, a first oxide layers and amorphous silicon layer, and a second oxide layer. The method includes depositing a sacrificial layer on the substrate. A trench is patterned an etched through the sacrificial layer. A conductor is deposited into the trench and the sacrificial layer is removed. A third oxide layer is deposited adjacent to the conductor. At least one wordline is formed adjacent the conductor. As a result of the method, the conductor is self-aligned with the amorphous polysilicon layer.
The invention, in another form thereof, is a method of programming an EEPROM device having a program gate and floating gate. The method includes selectively turning on and off at least one wordline and applying a voltage to the program gate whereby permitting electron tunneling between the program gate and the floating gate.
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Y. Ma et al., A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless ARray for Single-Vcc High Densi
Chen Bomy A.
Harrington Jay G.
Houlihan Kevin M.
Hoyniak Dennis
Lam Chung Hon
Eckert II George C.
International Business Machines - Corporation
Lee Eddie
McGinn & Gibb PLLC
Neff Daryl K.
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