Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-30
2004-10-12
Kielin, Eric (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000
Reexamination Certificate
active
06803283
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method to form ROM devices and, more particularly, to a method to form ROM devices wherein the coding of each ROM cell is controlled by the LDD and source/drain, ion implantation steps.
(2) Description of the Prior Art
Data storage devices are used in a variety of integrated circuits applications. A particularly important type of data storage device is the read-only memory (ROM). In a ROM device, data is permanently coded into the memory array for later read-out. By comparison, in a RAM device, the data may be altered during subsequent operation of the memory. ROM memory is typically used for the storage of computer programs and other information that will never require altering during the operating life of the application system. Where the system requires alterable memory, RAM memory or Flash memory may be included to provide changeable memory arrays that are either lost or retained, respectively, upon power down.
Typically, the ROM data is programmed into the device during the integrated circuit manufacturing process. Because of the relatively long cycle time required for integrated circuit fabrication, the system designer must provide the circuit fabricator with the final program data well in advance of the completion of manufacture. This fact tends to reduce the available system design time. At the same time, the manufacture attempts to fabricate the device in such a way as to delay the required program coding as long as possible to thereby maximize the system design time.
Referring now to
FIG. 1
, an exemplary, prior art ROM integrated circuit device is shown. More particularly, a simplified cross-section of a ROM device is shown at an intermediate step in the fabrication process for a ROM array. The ROM array comprises a large number of ROM devices formed in a substrate
10
. In the cross-section, two partially complete devices are shown. A first device
50
and a second device
60
are being formed in active areas of the substrate
10
. The active areas of the substrate
10
are separated by field oxidation regions (FOX)
20
. Two MOS gates
25
, comprising polysilicon
34
overlying oxide
30
, have been formed in the active areas for the first device
50
and for the second device
60
.
Referring now to
FIG. 2
, a further step in processing in shown. Assuming a sub-micron process where short channel effects must be considered, an ion implantation
64
is performed to form lightly doped drains (LDD)
68
in the substrate. Note that this implantation is blocked from unwanted areas in the circuit device by a masking layer
66
. However, in the array devices
50
and
60
, the LDD ion implantation
64
is a blanket implant. The MOS gates
25
block ions from the channel region of the devices such that the LDD regions
68
are self-aligned to the gates
25
.
Referring now to
FIG. 3
, yet further steps in conventional processing are shown. After spacers
76
are formed on the sidewalls of the gates
25
, another ion implantation is performed
84
. This ion implantation
84
forms source and drain regions
88
in the substrate for the ROM devices
50
and
60
. The implantation
84
is again blocked from unwanted areas by a masking layer
80
. The combination of the MOS gates
25
and the spacers
76
cause the source/drain regions
88
to be self-aligned to the spacers
76
.
The resulting devices
50
and
60
are recognizable as MOS transistors. A typical data storage mechanism for such a MOS-based, ROM array is the threshold voltage of the devices. The threshold voltage is defined as the gate-to-source voltage at which a conductive channel is formed, by inversion, such that the device is in the ON-state. This threshold voltage is coded into each device in the array by a subsequent manufacturing process as will be discussed below. In the ROM, additional circuitry is used to select particular transistors in the array and to read the value of the data stored thereon by monitoring current flow in the device in response to a standard gate-to-source voltage.
Referring now to
FIG. 4
, a typical method for storing the threshold voltage in each cell in the array is shown. A ROM code, ion implantation
104
is performed on the array. Ions are implanted
104
into the substrate
10
through selected gates
25
in the array. A masking layer
100
is used to control which ROM cells
50
receive the implant
104
and which ROM cells
60
do not receive the implant
104
. Where the masking layer
100
is open, ions penetrate the gate
25
and form a doped region
110
in the substrate
10
. Where the masking layer
100
covers a gate
25
, ions cannot penetrate, and no doped region is formed
120
.
For example, if the ROM array comprises NMOS devices, then the substrate
10
will be lightly-doped P-type, the LDD regions
68
will be doped n-type, and the source/drain regions
88
will be heavily doped n-type. In this exemplary case, the coding implant
104
increases the p-doping
110
in the channel region of the implanted transistor
50
. This will effectively increase the threshold voltage of the device
50
. If the implant dose is made sufficiently high, the p-coded region
110
will cause the threshold voltage of the coded device
50
tobe too high to be turned ON by the available gate-to-source voltage of the operating ROM device. In this case, the coded ROM cell
50
is programmed ‘OFF’ or constant-OFF. By comparison, the non-coded device
60
has a low threshold voltage and can be turned-ON by the standard gate-to-source voltage of the operating ROM device. In this way, a part of the available ROM devices is programmed to ‘0’ while another part of the device array is programmed to ‘1’.
While the above-described method for forming and coding the ROM will work, there are several drawbacks. First, to form a ROM array out of a MOS device array, the method requires an additional photolithographic layer and an ion implantation step for p-coding. Second, if the MOS gate
25
is too thick, it is not possible to implant the p-code after the gate is formed. If the p-code must be implanted earlier in the process, this increases the cycle time or, conversely, reduces the available system design time.
Recently, manufacturers have developed methods to convert Flash memory device arrays into ROM arrays. This is a particularly useful technique for allowing the system designer to develop a first generation system using the alterable Flash array and then to convert the Flash array to a ROM array when the system program has been finalized. These Flash-ROM or FlashROM devices are Flash arrays in which relatively simple layout changes in the mask set will rapidly transform the Flash array product into a ROM array product while providing the same pin-out and access performance. In this FlashROM scenario, the MOS gate
25
is originally a Flash gate, comprising a stacked floating gate and control gate. However, the Flash gate is changed in to a simple MOS gate
25
during the Flash-to-ROM conversion process by modifying several masking layers. The p-coding layer is then added to the masking set for programming the ROM devices. A significant object of the present invention is to reduce the cost and timing impact of the formation of such ROM arrays, especially in the FlashROM case.
Several prior art inventions relate to methods to form and to code ROM devices. U.S. Pat. No. 6,020,241 to You et al discloses a mask ROM process. This method allows a ROM to be manufactured up to the metal processes prior to committing to a program code. The method uses a selective ion implantation through preformed openings to code the ROM array. U.S. Pat. No. 6,238,983 to Chu et al describes a method to code ROM cells. Selected ROM cells are dipped back to remove part of a poly-oxide layer overlying the gate. The ROM cells are then ion implanted through the gate to code enhancement or depletion mode. U.S. Pat. No. 5,514,610 to Wann et al teaches a method to code ROM cells. Ions are implanted into through ROM gates after a screen oxide is
Kielin Eric
Taiwan Semiconductor Manufacturing Co. Ltd.
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