Method, system, and apparatus for bit error capture and...

Details Method, system, and apparatus for bit error capture and... Method, system, and apparatus for bit error capture and...

2007-01-16

2007-01-16

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S761000, C714S765000

Reexamination Certificate

active

10641613

ABSTRACT:
An apparatus and method to facilitate validation and/or test of serial interfaces by analyzing error event types based at least in part on a code-stamp, compare engine logic and a memory for error capture.

REFERENCES:
patent: 4342084 (1982-07-01), Sager et al.
patent: 5615335 (1997-03-01), Onffroy et al.
patent: 5832047 (1998-11-01), Ferraiolo et al.
patent: 6185693 (2001-02-01), Garmire et al.
patent: 6754858 (2004-06-01), Borkenhagen et al.

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