Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-01
2009-02-17
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S005000
Reexamination Certificate
active
07493589
ABSTRACT:
A method of decomposing a target pattern having features to be imaged on a substrate so as to allow said features to be imaged in a multi-exposure process. The method includes the steps of: (a) segmenting a plurality of the features into a plurality of polygons; (b) determining the image log slope (ILS) value for each of the plurality of polygons; (c) determining the polygon having the minimum ILS value, and defining a mask containing the polygon; (d) convolving the mask defined in step (c) with an eigen function of a transmission cross coefficient so as to generate an interference map, where the transmission cross coefficient defines the illumination system to be utilized to image the target pattern; and (e) assigning a phase to the polygon based on the value of the interference map at a location corresponding to the polygon, where the phase defines which exposure in said multi-exposure process the polygon is assigned.
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ASML Masktools B.V.
Chiang Jack
Dimyan Magid Y
Pillsbury Winthrop Shaw & Pittman LLP
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