Method of verifying the power off effect of a design entity...

Details Method of verifying the power off effect of a design entity... Method of verifying the power off effect of a design entity...

2006-08-18

2008-08-19

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S002000, C703S016000

Reexamination Certificate

active

07415685

ABSTRACT:
A method of verifying the power off effect of a design entity of a digital system includes a device model, a test input signal model, and a test output signal model specified in a hardware design language, at a register transfer level (RTL). The device model describes function blocks for performing predetermined functions using a plurality of power sources. The device model includes a model for a case where all of the power sources are supplied and a model for a case where one or more of the power sources are blocked. The test input signal model describes a test input signal to be input to the device model to verify the case where all of the power sources are supplied and the case where one or more of the power sources are blocked. The test output signal model describes a test output signal to be output from the device model in response to the test input signal.

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