Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-17
2003-04-22
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S262000, C438S287000, C438S595000
Reexamination Certificate
active
06551880
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a fabricating method of metal oxide nitride oxide semiconductor or (MONOS) or semiconductor oxide nitride oxide semiconductor (SONOS) and, more particularly, to a method of using a discontinuous oxide nitride oxide (ONO) structure as floating gate spacers to build twin-bit MONOS/SONOS memory.
BACKGROUND OF THE INVENTION
Along with current advancement of information products, MONOS or SONOS memories tend toward high speed and compactness. For memory devices widely used in electronic products, conventional electrically erasable and programmable read only memories (EEPROMs) have the drawback of slower speed of access. However, along with progress of process technology, EEPROMs with faster speed of access, generally called flash memories, have been developed.
Basically, conventional flash memories are nonvolatile memories with floating gate transistors as the basis. In the memory cell of each flash memory, a source and a drain are formed in a semiconductor substrate, respectively. Next, an oxide, a nitride, and an oxide (an ONO structure) are formed in turn on the surface of the semiconductor substrate between the source and the drain, thereby forming a floating gate for storing charges. A control gate for controlling access of data is then formed above the ONO structure.
The state of a flash memory depends on the charge density of the floating gate, and the operation thereof depends on the technique of injecting charges into or removing charges from the floating gate. Therefore, when program data is written in, a high voltage is applied to the control gate to let hot electrons pass through the oxide from the drain and be injected into the nitride of the floating gate, hence enhancing the threshold voltage to write in data. When erasing data, it is only necessary to complete the operation of erase by means of hot hole injection to let holes enter the nitride of the floating gate and reach the same positions of the above electrons to compensate the electrons, hence achieving the object of erase.
However, in a MONOS/SONOS memory device exemplified by the above flash memory, each memory unit can only store a bit. Or each memory unit can store two bits, but there is cross talk between charges stored in these two bits, hence reducing the reliability of device. Moreover, in the prior art continuous structure, if electrons are trapped in the channel, it is difficult for two ends of the channel to restore its normal characteristics, thus failing the device. Therefore, to resolve the problems in the prior art, the present invention provides a fabricating method of a twin-bit MONOS/SONOS memory. Discontinuous ONO control gate spacers are fabricated below a control gate to build a twin-bit MONOS/SONOS memory to avoid cross talk between stored charges and to enhance the reliability of device. Furthermore, if the voltage V
t
varies during the fabrication process (e.g., when electrons are trapped in a silicon nitride (SiN)), the device can restore its normal characteristics through the individual and separate characteristic of the two bits and by using program or erase condition.
SUMMARY OF THE INVENTION
The primary object of the present invention is to provide a fabricating method of memory device, wherein the fabrication process of ONO floating gate spacer is utilized to fabricate a twin-bit MONOS/SONOS memory so that a discontinuous floating gate can be built in a single MONOS/SONOS device as a twin-point type charge-storing region to double the capacity of memory, hence increasing the capacity of a memory device.
Another object of the present invention is to fabricate a MONOS/SONOS memory capable of storing two bits to avoid cross talk between charges stored in the two bits, hence enhancing the reliability of memory device. Moreover, if the voltage V
t
varies during the fabrication process, the device can restore its normal characteristics through the individual and separate characteristic of the two bits and by using program or erase condition, thereby resolving the problem that it is difficult for two ends of a channel to restore their normal characteristics so as to fail the device if electrons are trapped in the channel in the prior art continuous structure.
Yet another object of the present invention is to provide a fabricating method of twin-bit memories, wherein the fabrication process of ONO floating gate spacer is utilized to complete the fabrication process of floating gate in automatic alignment way without the need of undergoing several mask processes, hence saving the prior art lithography process and resolving its problem of misalignment.
According to the present invention, ion implantation is performed to a silicon substrate having a pad oxide with an already defined silicon nitride as a hard mask. An oxide is formed and its surface is planarized to remove the silicon nitride and the pad oxide. Next, an ONO film is deposited on the silicon substrate, and anisotropic etch is then performed to the ONO film to form recessed and symmetrical ONO spacers. Finally, a gate oxide is deposited and an already defined polysilicon is formed. A twin-bit MONOS/SONOS memory structure is thus formed.
REFERENCES:
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6432773 (2002-08-01), Gerber et al.
patent: 6458642 (2002-10-01), Yeh et al.
Chen Ying Tzoo
Huang Shou Wei
Liu Chien-Hung
Pan Shyi-Shuh
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