Method of using source/drain nitride for periphery field...

Details Method of using source/drain nitride for periphery field... Method of using source/drain nitride for periphery field...

1999-10-25

2001-03-27

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S591000

Reexamination Certificate

active

06207502

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of the dielectric layers in semiconductor devices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain.
A Flash device that utilizes the ONO structure is a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell. Referring to
FIG. 1
, a known MONOS type cell, generally referred to as
10
, includes at least one bit-line oxide
12
, a word line
14
and an ONO structure
16
which function together to determine the location of a charge stored in memory. The bit-line oxide
12
and the ONO structure
16
overlie a silicon wafer
17
.
A problem exists with known MONOS type cell fabrication techniques in that a formation of the bit-line oxide
12
causes a bird's beak
18
of the ONO structure
16
to form and increasingly encroach the word line
14
. The formation of the bird's beak
18
is aided by a thin nitride layer of the ONO structure which is typically only about
135
angstroms thick. The bird's beak
18
is an undesired result of the fabrication process for several reasons. For example, the bird's beak
18
causes an increase in surface area which enlarges the circuit. In addition, at a performance level, the bird's beak
18
can induce fatal stress damage to the silicon wafer
17
, especially during bit-line oxidation steps. The stress results, for example, from a mismatch in thermal expansion properties between the ONO structure
18
and the silicon wafer
17
.
Therefore, while recent advances in MONOS type cell technology have enabled memory designers to improve the MONOS type cells, numerous challenges exist in the fabrication of material layers within these devices. In particular, a reduction of a bird's beak formation of the MONOS type cell is required. Accordingly, advances in MONOS type cell fabrication technology are necessary to reduce the bird's beak and insure high quality MONOS type cell devices.
SUMMARY OF THE INVENTION
Such needs are met or exceeded by the present method for fabricating a MONOS type cell. According to an aspect of the present invention, an unwanted bird's beak feature of the MONOS type cell is reduced. Therefore, a higher quality is obtained for an ONO structure of the MONOS type cell.
More specifically, in one form, a process for fabricating a bit-line structure for a MONOS type cell includes providing a semiconductor substrate and growing a barrier silicon oxide layer to overlie semiconductor substrate. Thereafter, a thick silicon nitride layer is formed to overlie the barrier silicon oxide layer. A mask and etch are performed at the periphery of the MONOS type cell to form a trench in the semiconductor substrate. The periphery field oxide region is formed by depositing silicon oxide to fill the trench.
Thereafter, a mask and etch are performed at the core of the MONOS cell to form a trench in the semiconductor substrate. The bit-line oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, the thick silicon nitride layer is removed. Since the periphery field oxide region and bit-line region are formed before the thick nitride layer is removed, the formation of an unwanted bird's beak is reduced.


REFERENCES:
patent: 5496753 (1996-03-01), Sakurai et al.
patent: 5851881 (1998-12-01), Lin et al.
patent: 6103572 (2000-08-01), Kirihara

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