Method of using silicon rich carbide as a barrier material...

Details Method of using silicon rich carbide as a barrier material... Method of using silicon rich carbide as a barrier material...

2002-07-01

2004-05-04

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S627000, C438S629000, C438S630000, C438S687000, C438S688000, C438S931000

Reexamination Certificate

active

06730591

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to forming interconnect structures in semiconductor devices, and more specifically to methods of incorporating fluorinated amorphous carbon and fluorocarbon polymers in the formation of interconnect structures in semiconductor devices.
BACKGROUND OF THE INVENTION
The miniaturization of microelectronic devices and the need for higher speeds have created a demand for low dielectric constant (low-k) materials. Fluorinated amorphous carbon and fluorocarbon polymer films exhibit excellent low dielectric constant properties due to the incorporation of less polarizable fluorine atoms.
One of the primary concerns with these films is that they release fluorine upon heating. Materials, such as Ta, TaN, Ti, TiN, and Al, etc., in contact with these films may react with the fluorine and/or fluorine bearing species thereby compromising the interfacial adhesion between the films and materials.
Thus, a fluorine diffusion barrier is needed for the integration of fluorinated low-k materials.
U.S. Pat. No. 5,817,572 to Chiang et al. describes a method for forming interconnections for semiconductor fabrication and semiconductor devices. In one embodiment, a silicon carbide (SiC) etch barrier is used in a dual damascene process.
U.S. Pat. No. 5,744,817 to Shannon describes a hot carrier transistor and a method of making a hot carrier transistor wherein the emitter region films
20
a
,
20
b
may comprise silicon-rich amorphous silicon carbide.
U.S. Pat. No. 5,736,457 to Zhao describes a method of making a single or dual damascene process where an IMD layer
105
may be comprised of SiC.
U.S. Pat. No. 3,830,668 to Dearnaley et al. describes a method of forming electrically insulating layers in semi-conducting materials. A block of SiC is irradiated with protons to form a layer or radiation damage and releases a certain amount of carbon impurity atoms from their substitutional-sites. The structure is irradiated with low energy electrons and then annealed in which the released carbon atoms migrate and precipitate in the region of the radiation-damaged layer.
U.S. Pat. No. 5,891,803 to Gardner describes a dual damascene process with a dielectric layer
340
that may be comprised of SiC.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming a barrier layer for use with fluorinated dielectric layers and/or intermetal dielectric layers (IMDs).
Another object of the present invention to provide a method of forming a barrier layer for use with fluorinated dielectric layers and/or intermetal dielectric layers (IMDs) that blocks diffusion of fluorine through the barrier layer.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a fluorinated dielectric layer is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer is formed over the semiconductor structure. The fluorinated dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.


REFERENCES:
patent: 3830668 (1974-08-01), Dearnaley et al.
patent: 5736457 (1998-04-01), Zhao
patent: 5744817 (1998-04-01), Shannon
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5818071 (1998-10-01), Loboda et al.
patent: 6297149 (2001-10-01), Stamper
patent: 6413854 (2002-07-01), Uzoh et al.

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