Method of trimming technology

Details Method of trimming technology Method of trimming technology

2008-04-08

2008-04-08

Lee, Calvin (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C257S202000

Reexamination Certificate

active

10764913

ABSTRACT:
A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2and SO2chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2by a HBr/O2/Cl2plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2chemistry. The underlayer is stripped by an O2ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

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