Method of transparently reducing power consumption of a...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

Reexamination Certificate

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C327S544000, C327S530000, C326S080000

Reexamination Certificate

active

07443195

ABSTRACT:
A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

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AR Wei-Hung Chen, Guang-Kaai Dehng, Jong-Woei Chen and Shen-Iuan Liu,A CMOS 400-MB/s Serial Link for AS-Memory Systems Using a PWM Scheme, IEEE Journal of Solid State Circuits, vol. 36, Issue 10, Oct. 2001 pp. 1498-1505.
AS Chih-Kong Ken Yang, Ramin Farjad-Rad and Mark A, Horowitz,A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver With Data Recovery Using Oversampling, IEEE Journal of Solid State Circuits, vol. 33, Issue 5, May 1998, pp. 713-722.
AT John M. Khoury and Kadaba R. Lakshmikumar,High-Speed Serial Transceivers for Data Communication Systems, IEEE Communications Magazine, vol. 39, Issue 7, Jul. 2001, pp. 160-165.

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