Method of testing a semiconductor memory device

Details Method of testing a semiconductor memory device Method of testing a semiconductor memory device

2001-01-18

2004-03-30

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06715117

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for testing a semiconductor memory device, and more particularly to a method for testing a semiconductor memory device by use of a test circuit having, for example, the semiconductor memory device to be tested and logic circuits mounted thereon.
2. Description of the Related Art
FIG. 10
is a circuit diagram showing the configuration of a test circuit employed by a conventional method for testing a semiconductor memory device.
In the figure, reference numeral
5
denotes a test circuit for testing a DRAM
52
having a capacity of 16 Mbits, and the test circuit
5
is connected to a testing device (hereinafter referred to as a tester) not shown. Reference numeral
51
denotes an 8-bit D flip-flop which receives 8-bit input data TDI output from the tester through its input D (7:0) and holds the data upon a rise of a write clock signal TWCK. The output Q (7:0) of the 8-bit D flip-fop
51
is controlled according to an output control signal TOE-.
Reference numeral
52
indicates a 16 Mbit DRAM (Dynamic Random Access Memory) used as a semiconductor memory device sample to be tested, and has a wide data bus of, for, example, an (m×n)-bit width—in the example of
FIG. 10
, m=8 (bits) and n=16 (stages), totaling 128 bits. There are 4096 row addresses and 32 column addresses, that is, a 12-bit row address line and a 5-bit column address line, respectively, totaling 17 bits for the row and column address lines.
Reference numeral
53
denotes a 128-to-8 multiplexer which reads (8×16)-bit data from the 16 Mbit DRAM
52
, selects a set of an 8-bit data from the read (8×16)-bit data based on an output data selection signal TSEL fed from the tester, and outputs the selected 8-bit data as an 8-bit output data TDO.
The number 4, 8, or 17 given to each line indicates the number of data bits employed for the line, and the bracketed numbers <0> to <15> each indicate corresponding an 8-bit data.
The operation of the test circuit will be explained below.
Description will be first made of write operation to the 16 Mbit DRAM
52
.
The input data TDI output from the tester is input to the input D (7:0) of the D flip-flop
51
, and held upon a rise of a write clock signal TWCK. At that time, when the tester outputs an output control signal TOE- having a high level (H level signal) so as to apply the H level signal to the OE terminal of the D flip-flop
51
, an 8-bit data is output from the output Q (7:0) of the D flip-flop
51
.
The data output from the output Q (7:0) of the D flip-flop
51
branches out into
16
sets of data each having 8 bits. Then, the tester enters an address signal TADI, which indicates a row address and a column address, and an address strobe signal TAS- having a low level (an L level), to the corresponding terminals of the 16 Mbit DRAM
52
. The current address signal TADI is introduced into the 16 Mbit DRAM
52
at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the 16 Mbit DRAM
52
, the tester outputs a write control signal TW- having an L level, and as result, the data which has branched out into the 16 sets of data each having 8 bits is written into a memory area in the 16 Mbit DRAM
52
specified by the address signal TADI through a terminal D (127:0). At that time, since an output control signal TOE- having an H level is fed to the 16 Mbit DRAM
52
, the output of the 16 Mbit DRAM
52
is disabled.
Next, description will be made of read operation from the 16 Mbit DRAM
52
.
The tester enters an address signal TADI, which indicates a row address and a column address, and an address strobe signal TAS- having an L level, to the corresponding terminals of the 16 Mbit DRAM
52
. The current address signal TADI is introduced into the 16 Mbit DRAM
52
at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the 16 Mbit DRAM
52
, the tester outputs an output control signal TOE- having an L level, and as result, (8×16)-bit data which has been written into a memory area in the 16 Mbit DRAM
52
specified by the introduced address signal TADI is read out at the same time. At that time, since the tester outputs a write control signal TW- having an H level and an output control signal TOE- having an L level, both write operation to the 16 Mbit DRAM
52
and output from the output Q (7:0) of the D flip-flop
51
are disabled.
The multiplexer
53
selects a set of 8-bit data from (8×16)-bit data delivered from the output Q (127:0) of the 16 Mbit DRAM
52
based on an output data selection signal TSEL entered from the tester, and outputs the selected set of 8-bit data as an output data TDO.
Description will be made of the procedure of a conventional method for testing a semiconductor memory device using the above test circuit.
FIG. 11
is a flowchart showing the procedure of a conventional method for testing a semiconductor memory device. It is assumed that the 16 Mbit DRAM
52
having a wide data bus of an (m×n)-bit width has a row address size of x and a column address size of y.
To begin with, (m×n)-bit data entered from the tester is fed to the input D (7:0) of the D flip-flop
51
in units of m bits sequentially as input data TDI, and delivered from the output Q (7:0) when the output control signal TOE- is at an H level. Then, the tester sets the row address X and the column address Y so that X=0 and Y=0, at step ST
100
.
To write the data into the 16 Mbit DRAM
52
, the tester enters an address signal TADI indicating that the row address X=0 and the column address Y=0, and an address strobe signal TAS- having an L level to the corresponding terminals of the 16 Mbit DRAM
52
. The current address signal TADI is introduced into the 16 Mbit DRAM
52
at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the DRAM
52
, the tester outputs a write control signal TW- having an L level, and as a result, the (m×n)-bit data is written into a memory area (X=0, Y=0) in the 16 Mbit DRAM
52
specified by the address signal TADI at step ST
101
.
To read out the data written into the 16 Mbit DRAM
52
, the tester enters an address signal TADI indicating that the row address X=0 and the column address Y=0, and an address strobe signal TAS- having an L level to the corresponding terminals of the 16 Mbit DRAM
52
. The current address signal TADI is introduced into the 16 Mbit DRAM
52
at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the DRAM
52
, the tester outputs an output control signal TOE- having an L level, and as a result, the (8×16)-bit data which has been written into the memory area (X=0, Y=0) in the 16 Mbit DRAM
52
specified by the introduced address signal TADI is read out at the same time at step ST
102
. The multiplexer
53
selects m-bit data indicated by a number N of
0
from the read-out n sets of m-bit data according to an output data selection signal TSEL delivered from the tester, and outputs the selected m-bit data as output data TDO at step ST
103
. The tester receives the output data TDO, and compares it with an expected value of the corresponding m-bit data to determine whether the output data TDO is correct at step ST
104
.
If it is determined that the output data TDO is erroneous, the tester obtains the corresponding defective bit information (indicating that the row address X=0, the column address Y=0, and the number N given to the compared m-bit data=0) at step ST
105
. Then, to test the next m-bit output data TDO, the tester adds 1 to the number N given to the current m-bit data at step ST
106
, and determines whether the number N is equal to or larger than n at step ST
107
. On the other hand, at step ST
104
, if it is determined

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