Method of testing a memory module and hub of the memory module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S731000, C714S715000, C714S025000, C714S030000, C714S042000, C714S048000, C714S719000, C714S733000, C714S734000, C714S735000, C714S736000, C714S742000, C365S201000, C330S255000, C330S051000, C326S086000, C327S397000

Reexamination Certificate

active

08051343

ABSTRACT:
Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

REFERENCES:
patent: 5432476 (1995-07-01), Tran
patent: 6070255 (2000-05-01), Dell et al.
patent: 6233182 (2001-05-01), Satou et al.
patent: 6664851 (2003-12-01), Pihlstrom et al.
patent: 6683484 (2004-01-01), Kueng et al.
patent: 6754117 (2004-06-01), Jeddeloh
patent: 6819142 (2004-11-01), Viehmann et al.
patent: 6996749 (2006-02-01), Bains et al.
patent: 7197684 (2007-03-01), Fang et al.
patent: 7210059 (2007-04-01), Jeddeloh
patent: 7212423 (2007-05-01), Vogt
patent: 7266633 (2007-09-01), James
patent: 7356742 (2008-04-01), Aoki et al.
patent: 7400173 (2008-07-01), Kwong et al.
patent: 7412627 (2008-08-01), Bains et al.
patent: 7434118 (2008-10-01), Moessinger et al.
patent: 2002/0078408 (2002-06-01), Chambers
patent: 2002/0093874 (2002-07-01), Ukon
patent: 2004/0070451 (2004-04-01), Pihlstrom et al.
patent: 2004/0246786 (2004-12-01), Vogt
patent: 2005/0060600 (2005-03-01), Jeddeloh
patent: 2005/0105350 (2005-05-01), Zimmerman
patent: 2005/0259480 (2005-11-01), Bains et al.
patent: 2005/0283681 (2005-12-01), Jeddeloh
patent: 2006/0218331 (2006-09-01), James
patent: 2007/0124548 (2007-05-01), Vogt
patent: 103 35 978 (2005-03-01), None
patent: 2001-0083784 (2001-09-01), None
patent: WO 2004/017162 (2004-02-01), None
Chinese Office Action dated Feb. 16, 2009 for corresponding Chinese Patent Application No. 2005100778860.
JEDEC Standard “Fully Buffered DIMM (FBDIMM): DFx Design for Validation and Test”, Jedec Solid State Technology Association, JESD82-28 (Feb. 2008).
Jeddeloh, Joe: Fully Buffered (FB Dimm), JEDEX, San Jose, Apr. 15-16, 2004, conference documents from the Internet (status as of May 2, 2007) http://download.micron.com/pdf/presentations/jedex/fbdimm—micron—2004.pdf.
JEDEC Standard No. 82-20: “FBDIMM:Advanced Memory Buffer (AMB)”, JEDEC Mar. 2007.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of testing a memory module and hub of the memory module does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of testing a memory module and hub of the memory module, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of testing a memory module and hub of the memory module will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4277965

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.