Method of stress-testing an isolation gate in a dynamic...

Details Method of stress-testing an isolation gate in a dynamic... Method of stress-testing an isolation gate in a dynamic...

2007-02-20

2007-02-20

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S190000, C365S200000

Reexamination Certificate

active

11171872

ABSTRACT:
The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.

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