Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1998-12-18
2004-08-31
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S257000, C438S275000, C438S766000, C438S911000
Reexamination Certificate
active
06784115
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a read only memory (“ROM”) cell, and more particularly to the manufacture of a flash electrically-erasable programmable read only memory (“Flash EEPROM”) cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as mask ROMs, embedded Flash EEPROMs, embedded DRAMs, microcontrollers, microprocessors (“MICROs”), digital signal processors (“DSPs”), application specific integrated circuits, among others.
Read only memories (ROMs) and various methods of their manufacture have been used or proposed. In the fabrication of a ROM, particularly an EEPROM, it is often necessary to fabricate a storage cell that maintains data after the applied power is turned off, that is, a storage cell having almost permanent data characteristics. The storage cells are generally mass data storage files where each cell corresponds to the presence or absence of a stored charge on a “floating” gate of a storage cell transistor. Specifically, the storage cell includes at least two conducting layers—one conducting layer is the floating gate of the storage cell transistor, and another conducting layer is the control gate for control of the cell operation. The floating gate is formed on a thin gate oxide formed on the substrate. The control gate is located above the floating gate, and the control gate and floating gate are isolated from each other by a thin dielectric layer known as an “interpoly oxide”, which may typically be composed of oxide
itride/oxide (“ONO”). In some typical EEPROMs, data are programmed into the cells by applying a high voltage to the control gate to inject hot electrons (or tunnel electrons in some devices) into the floating gate. The process of programming data is often called coding. In coding, the charge is transferred from the silicon substrate through the thin gate oxide layer to the floating gate.
In typical EEPROMs, especially for flash EEPROMs, two different gate oxide thicknesses are generally required for optimized device performance. In such devices, it is often critical to grow a high-quality, thin gate oxide (used as a tunneling oxide) in the storage cell and (used as a gate oxide) in some transistors in the periphery of the storage cell region in order to provide high driving capability for higher speed. Controlling the thickness of the thin gate oxide is crucial, especially since design rules for devices with gates are becoming increasingly smaller and require thinner gate oxides. Because high-voltage supplies are used, thicker gate oxides at the periphery of the storage cell region are needed to maintain device quality and reliability after long-term high voltage stress from the high voltages (e.g., up to or greater than ±12V) generated through a pumping circuit for the storage cell coding and/or erase. Therefore, implementing different gate oxide thicknesses in EEPROM devices is an important aspect of the fabrication of high performance devices.
Conventional methods for forming different gate oxide thicknesses in ROMs have typically involved the use of photoresist in combination with a dry or wet etch step. First, a gate oxide is grown on a silicon substrate then masked with a photoresist. The photoresist used makes physical contact with and masks a portion of the gate oxide, while the etch step completely removes a portion of the gate oxide to provide exposed substrate. Such photoresist typically contains many contaminants which degrade the ability of the gate oxide to resist long-term high voltage stresses. Then another oxidation process is performed to provide a thin oxide layer on the exposed substrate and a thicker oxide layer where the masked gate oxide was located. Use of a dry etch creates the possibility of over-etching of the gate oxide down to the silicon substrate to cause damage to the substrate and degrade the quality of the thin gate oxide layer grown on the exposed substrate. The use of a dry etch may also present problems for oxide thickness control. Further, the use of two separate oxidation steps in forming the different gate oxide thicknesses often results in slower throughput, which is inefficient for economically manufacturing high quality devices. From the above it is seen that an improved method of fabricating semiconductor devices with a reliable, high-quality gate oxide having different thicknesses is often desired. Further, more efficient methods are needed which are able to provide with adequate thickness control high-quality gate oxides, especially for increasingly smaller device dimensions, that are sufficiently thin in certain regions such as the cell regions and thicker in other regions such as periphery regions.
SUMMARY OF THE INVENTION
The present invention provides an improved method and resulting structure for an integrated circuit device. In particular, the present invention provides an improved integrated circuit and method of manufacture therefor using a novel technique that relies upon a halogen bearing impurity, e.g., fluorine, chlorine, iodine, and bromine.
In a specific embodiment, the present invention provides a method of forming a semiconductor device. The method includes the steps of providing a semiconductor substrate having a first region where a first oxide layer thickness is desired and a second region where a second oxide layer thickness is desired, and introducing halogen-containing impurities (e.g., fluorine, chlorine, bromine, iodine, or any combination thereof) into the semiconductor substrate to form a higher halogen concentration in the first region than in the second region. The method also includes the step of performing an oxidizing process on the semiconductor substrate to simultaneously form a thermal gate oxide layer having the first oxide layer thickness at the first region and the second oxide layer thickness at the second region, where the first oxide layer thickness is thicker than the second oxide layer thickness. Additional regions can also be formed using other concentrations and/or impurities to provide a structure with more than two (e.g., three, four, five, six) differing oxide or dielectric layers.
According to an alternative embodiment, the present invention provides a method of forming a semiconductor integrated circuit. The method includes the step of providing a semiconductor substrate. The semiconductor substrate includes a memory cell region, a second region for a MOS transistor, and a first region for a high voltage device. The method also includes the steps of forming a gate dielectric layer comprising an oxide overlying the semiconductor substrate including the first region and the second region, selectively implanting fluorine-containing impurities (or impurities such as chlorine, bromine, iodine, or any combination thereof) into the first region, and simultaneously forming a first thickness of dielectric material overlying the first region and forming a second thickness of dielectric material overlying the second region. The first thickness is sufficiently thick to provide high driving capability and reliability for the high voltage device, and the second thickness is sufficiently thin to provide for switching of the MOS transistor. Additional regions can also be formed using other concentrations and/or impurities to provide a structure with more than two (e.g., three, four, five, six) differing oxide or dielectric layers.
According to another embodiment, the present invention provides an integrated circuit such as a flash EEPROM semiconductor device. The device includes a semiconductor substrate, a first memory gate electrode formed on a first gate oxide layer on the semiconductor substrate with the first memory gate electrode having a width of about 0.35 &mgr;m or less, and a second gate oxide layer having a first thickness and a second thickness
Chang Chih-Sheng
Liu Jacson
Ni Cheng-Tsung
Wu Hudy-Jong
Fourson George
Garcia Joannie Adelle
Mosel Vitelic Inc.
Townsend and Townsend / and Crew LLP
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